Although the number of pixels in image sensors is increasing exponentially, production techniques have only been able to linearly reduce the probability that a pixel will be defective. The result is a rapidly increasing probability that a sensor will contain one or more defective pixels. The defect pixel detection and defect pixel correction are operated separately but the former must employ before the latter is in use. Traditional detection scheme, which finds the defect pixels during manufacturing, is not able to discover the spread defect pixels years late. Consequently, the lifetime and robust defect pixel detection technique, which identifies the fault pixels when camera is in use, is more practical and developed. The paper presents a two stages dead pixel detection technique without complicated mathematic computations so that the embedded devices can easily implement it. Using six dead pixel types are tested and the experimental result indicates that it can be accelerated more than four times the detection time.
The three-dimensional (3-D) stacking memory is good way to extend the local memory of embedded CPU and/or DSP by the through-silicon-vias (TSVs) technology. In this work, we show a multi-core system with 3-D stacking memory, and the stacking memory can be configured as instruction cache or local data memory for each DSP core. Due to the noncacheable property of local memory, the programmers have to rethink the software algorithm and the data structure to efficiently use the extended memory space. To demonstrate the performance enhancement of 3-D system, this paper presents three enhanced multimedia applications for HW/SW cosimulation by the electronic system-level (ESL) virtual platform. According to the experimental results, the 3-D system performance can be improved by 30%~50% for assembly coded single-channel H.264 decoder and multichannel H.264 decoder respectively, compared with traditional 2-D system. In addition, for a JPEG decoder compiled with C compiler, more than 6 times system performance can be improved by placing the data section, heap and stack structure from external DDR2 memory to the 3-D stacking memory.
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