Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.

Memristors show great potential for being integrated into CMOS technology and provide new approaches for designing computing-in-memory (CIM) systems, brain-inspired applications, trimming circuits and other topologies for the beyond-CMOS era. A crucial characteristic of the memristor is multi-state 1 switching. Memristors are capable of representing information in an ultra-compact fashion, by storing multiple bits per device. However, certain challenges remain in multistate memristive circuits and systems design such as device stability and peripheral circuit complexity. In this paper, we review the state of the art of multi-state memristor technologies and their associated CMOS/Memristor circuit design, and discuss the challenges regarding device imperfection factors, modelling, peripheral circuit design and layout. We present measurement results of our in-house fabricated multi-state memristor as an example to further illustrate the feasibility of applying multistate memristors in CMOS design, and demonstrate their related future applications such as multi-state memristive memories in machine learning, memristive neuromorphic applications, trimming and tuning circuits, etc. In the end, we summarize past and present efforts done in this field and envisage the direction of multi-state memristor related research.

RRAM technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate with examples an end-to-end design flow for RRAM-based electronics, from the introduction of a custom RRAM model into our chosen CAD tool to performing layoutversus-schematic and post-layout checks including the RRAM device. We envisage that this step-by-step guide to introducing RRAM into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with RRAM-enhanced systems.

In general, intelligent systems require knowledge databases storing memory associations for mimicking the capabilities of the human brain. Conventional associative memory cells are constructed based on SRAM, a type of volatile memory consisting of large numbers of transistors per stored bit. Here, we present an energy efficient, robust and hardware friendlyassociative memory cell design that we designate RC-XNOR-Z. It is based on creating a tuneable RC constant with the help of a modifiable resistance element (RRAM), plus a simplified XNOR gate for generating the output. The overall design has a total component count of 6T1C1R (6 transistors, 1 capacitor, 1 RRAM device), is non-volatile, is designed to work with RRAM devices with very low ON/OFF ratio (≈4), avoids high current DC paths during misses and operates under power supply of 0.95V. Furthermore, we show expected simulated power dissipation per miss including refresh in the order of single-digit nW/bit and power dissipation/hit in the order of 10 µW, which for a clock rate of 1GHz translates into aJ and 100s of pJ dissipation accordingly. This is competitive with state of art DRAM and SRAM.

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