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This paper presents integration challenges on M1 to CT connection in Ultra low-k Back-End-Of-Line interconnects for 40nm node and beyond. In advance IC fabrication, porous dielectric materials, such as BDII (k~2.5), are used as insulator in copper interconnects for RC delay reduction. But the materials of inter-dielectric layer are still high density SiO2-based. The difference of physical properties in materials of ILD and IMD would potentially induce connection deterioration, which would further impact product yield by Contact open fail or other issues. Cross section pictures of failing point were exhibited with a special spacer profile to illustrate the phenomenon. Solutions were proposed, through optimization of Etch, Wet clean and CMP to improve process window. Layout optimization is also suggested as OPC and DFM solution for related layers. Solutions were examined by experiments with 40nm BEOL test masks. Results of physical and electric characterization were presented and discussed.

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