In this paper, we report the observation of the degradation and breakdown of thin silicon dioxide films subjected to both the unipolar and bipolar pulse voltage stresses at nanoscale by using conductive atomic force microscopy. It is found that the unipolar pulse voltage stress produces more severe damage than does the bipolar pulse voltage stress. We also notice that hard breakdown is always preceded by soft breakdown for thin silicon dioxide subjected to either unipolar or bipolar pulse voltage stress, and the soft breakdown is always accompanied with random current fluctuation in the I-t characteristics. The influence of varying frequency of the pulse voltage stresses on the oxide breakdown is also investigated in this work.

Conventionally, CoSi2 is considered to be a better choice than TiSi2 for integrated circuit fabrication due to its lower resisitivity and better thermal stability. In this letter we compare for the first time the stress reliability of metal–oxide–semiconductor (MOS) devices with CoSi2 and TiSi2 as gate electrode materials. We found that the use of TiSi2 as a gate electrode material can provide a better stress resistance than CoSi2, when negatively-biased constant current stress and constant voltage stress are applied.

Gate oxides prepared by repeated rapid thermal annealings of the thermal oxide in N2O ambient is proposed and metal–oxide–semiconductor (MOS) capacitors with these newly proposed gate dielectrics are studied. It is found that both the charge-to-breakdown and the oxide breakdown field shift to higher values as the number of repeated annealings and the annealing time increase. All the samples that have been subjected to repeated N2O rapid thermal annealings exhibit improved Fowler–Nordheim constant current stress resistance and radiation hardness when compared to the fresh sample and the conventional one-time N2O-annealed sample with a comparable annealing time. It is believed that this multiple N2O annealing method can be another promising candidate for fabricating hot-carrier resistant and radiation-hard MOS devices.

Lead halide perovskites have a wide range of application prospects in optoelectronic devices， including solar cells， light-emitting diodes(LEDs)， photodetectors， lasers， etc. However， the poor material stability and the inherent toxicity of lead have hindered its further commercialization. Therefore， all-inorganic lead-free halide perovskites and their derivatives have become one of the research hotspots. Cs 3 Cu 2 I 5 is a new all-inorganic lead-free halide perovskite derivative， which allows the possibility to be applied in a variety of fields due to its nontoxicity， ex• cellent optical properties and good stability under ambient conditions. This article introduces the various synthesis methods， physical properties and the applications in LEDs， ultraviolet photodetectors， scintillators and other fields of Cs 3 Cu 2 I 5 . In addition， the challenges and prospects of Cs 3 Cu 2 I 5 in optoelectronic fields are presented.

GOI (Gate Oxide Integrity) improvement in 65nm SAC OX (Sacrificial Oxide) free process integration was studied in this paper. After studying the effects of various processes in STI (Shallow Trench Isolation) module with SAC OX free scheme on GOI, it was found that the dominant process that could degrade GOI was the STI HDP (High Density Plasma) gap fill process. STI HDP gap fill process could cause Si damage on AA corners, also named as AA clipping, which will result in irregular corners and hence a thinner gate oxide formation at imperfect AA corners. This was observed by a TEM (transmission electron microscopy) study. In SAC OX free scheme, the exposed AA Si corners that were damaged during the HDP process did not get consumed and repaired while they would have gotten in the scheme with SAC OX and hence degraded GOI. By optimizing the STI gap fill processes and hardware configuration, the AA clipping can be greatly reduced and GOI can be improved to the required level.