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This study introduces a cyclical annealing technique that enhances the reliability of amorphous indium-gallium-zinc-oxide (a-IGZO) via-type structure thin film transistors (TFTs). By utilizing this treatment, negative gate-bias illumination stress (NBIS)-induced instabilities can be effectively alleviated. The cyclical annealing provides several cooling steps, which are exothermic processes that can form stronger ionic bonds. An additional advantage is that the total annealing time is much shorter than when using conventional long-term annealing. With the use of cyclical annealing, the reliability of the a-IGZO can be effectively optimized, and the shorter process time can increase fabrication efficiency.

This work demonstrates the generation of abnormal capacitance for amorphous indium-gallium-zinc oxide (a-InGaZnO4) thin-film transistors after being subjected to negative bias stress under ultraviolet light illumination stress (NBIS). At various operation frequencies, there are two-step tendencies in their capacitance-voltage curves. When gate bias is smaller than threshold voltage, the measured capacitance is dominated by interface defects. Conversely, the measured capacitance is dominated by oxygen vacancies when gate bias is larger than threshold voltage. The impact of these interface defects and oxygen vacancies on capacitance-voltage curves is verified by TCAD simulation software.

We control the nanoscale gaps on silver island films by different processing methods and investigate the surface-enhanced Raman scattering (SERS) efficiency on the films. We propose a facile technique to control the film morphology by substrate bending while keeping the evaporation rate constant. The films developed by our new method are compared to the films developed by traditional methods at various evaporation rates. The SERS signals generated on the samples prepared by the new method have similar strengths as the traditional methods. Substrate bending allows us to reduce the gap sizes while using a higher evaporation rate, hence the film can be developed in a shorter time. This cost-effective and time-efficient method is suitable for the mass production of large-area SERS sensors with good sensitivity. Scanning electron microscope images are analyzed to quantify the gap densities and widths to elucidate the relationship between the film morphology and the SERS intensity. While the gap size appears to be the major factor influencing the enhancement, the shape of the nano-island also seems to influence the SERS efficiency.

This paper introduces a method to determine the located region of trap position by the analysis of three-level random telegraph signal (RTS) in partially-depleted silicon-on-insulator n-channel metal-oxide-semiconductor field-effect-transistors. For the cases of two traps, the average time at the 2 nd level ( τ 2 ) is composed of average emission time of one trap and average capture time of the other. Comparison and analysis of τ 2 curves varying with gate voltage in RTS measurements with and without interchanged source/drain can clarify the located regions of the two traps. Moreover, the simplified equations are also considered and used to confirm the trap positions.Silicon-on-insulator (SOI) MOSFETs have been attracted attention recently due to their lower power consumption, high speed, increased circuit packing density and absence of CMOS latch-up. In addition, due to their power management characteristics and ability to switch to an improved operation speed in large-scale devices, SOI MOSFETs, memory devices, 1-3 and thin-film transistors (TFTs) 4-6 can be integrated into mobile electronic products. However, the floating body effect and self-heating effect 7-9 are inherent disadvantages in SOI devices. When devices are scaled down to deep sub-micrometer, the random telegraph signal (RTS) becomes a major issue and influences the performance of MOSFETs. 10-13 The RTS phenomenon is commonly caused by a carrier that has been captured and emitted by an oxide trap. Although researches on lateral trap position determined by 2-level channel current RTS (2-RTS) have been previously reported, [13][14][15] there are few reports that study the trap position in multilevel RTS. In this work, the located regions of lateral trap position are analyzed by 3-level channel current RTS (3-RTS) with and without interchanged S/D (reverse and forward operations). Then, according to the Shockley-Read-Hall (SRH) model, the located regions of the oxide trap are clarified by the comparisons between the average times at the medium channel current ( τ 2 ), or so-called the 2 nd level, under forward and reverse operations. Furthermore, the simplified equations, which are based on the SRH model, are used to confirm these trap positions. ExperimentalThe PD SOI nMOSFETs used in this study were fabricated by SOI technology with a T-gate structure. The thickness of silicon film and buried oxide are 0.15 μm and 1 μm, respectively. The gate oxide with thickness of 100 Å was grown on silicon film with a channel doping concentration of about 1.3 × 10 18 cm −3 . In this paper, the device has dimension of width/length = 1 μm/0.35 μm. The RTS measurements were performed by an Agilent B1500A semiconductor device analyzer, an Agilent B1530A Waveform-Generator/FastMeasurement-Unit (WGFMU) and a Cascade Microtech M150 measurement platform. Results and DiscussionFigure 1 shows the V G dependence on drain current RTS (I D -RTS) from V G = 0.45 V to 0.75 V with V D = 50 mV for a period of 100 * Electrochemical Society Active Member. z E-mail: tcchang3708@gma...