This Letter investigates a hump in gate current after negative-bias temperature-instability (NBTI) in HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors. Measuring gate current at initial through body floating and source/drain floating shows that hole current flows from source/drain. The fitting of gate current (Ig)-gate voltage (Vg) characteristic curves demonstrates that the Frenkel-Poole mechanism dominates the conduction. Next, by fitting the gate current after NBTI, in the order of Frenkel-Poole then tunneling, the Frenkel-Poole mechanism can be confirmed. These phenomena can be attributed to hole trapping in high-k bulk and the electric field formula Ehigh-k εhigh-k = Q + Esio2εsio2.

Articles you may be interested inInvestigation of extra traps measured by charge pumping technique in high voltage zone in p-channel metaloxide-semiconductor field-effect transistors with HfO2/metal gate stacks Appl. Phys. Lett. 102, 012106 (2013); 10.1063/1.4773914 Investigation of an anomalous hump in gate current after negative-bias temperature-instability in HfO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors Appl. Phys. Lett. 102, 012103 (2013); 10.1063/1.4773479 Analysis of anomalous traps measured by charge pumping technique in HfO2/metal gate n-channel metal-oxidesemiconductor field-effect transistors Characterization of fast charge trapping in bias temperature instability in metal-oxide-semiconductor field effect transistor with high dielectric constant Appl. Phys. Lett. 96, 142110 (2010); 10.1063/1.3384999 Anomalous negative bias temperature instability behavior in p -channel metal-oxide-semiconductor field-effect transistors with Hf Si O N Si O 2 gate stackThis letter investigates a hump in gate current after dynamic negative bias stress (NBS) in Hf x Zr 1-x O 2 /metal gate p-channel metal-oxide-semiconductor field-effect transistors. By measuring gate current under initial through body floating and source/drain floating, it shows that hole current flows from source/drain. The fitting of gate current-gate voltage characteristic curve demonstrates that Frenkel-Poole mechanism dominates the conduction. Next, by fitting the gate current after dynamic NBS, in the order of Frenkel-Poole then tunneling, the Frenkel-Poole mechanism can be confirmed. These phenomena can be attributed to hole trapping in high-k bulk and the electric field formula E high-k e high-k ¼ Q þ E sio2 e sio2 . V C 2012 American Institute of Physics. [http://dx.

This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

This letter investigates abnormal negative threshold voltage shifts under positive bias stress in input/output (I/O) TiN/HfO2 n-channel metal-oxide-semiconductor field-effect transistors using fast I-V measurement. This phenomenon is attributed to a reversible charge/discharge effect in pre-existing bulk traps. Moreover, in standard performance devices, threshold-voltage (Vt) shifts positively during fast I-V double sweep measurement. However, in I/O devices, Vt shifts negatively since electrons escape from bulk traps to metal gate rather than channel electrons injecting to bulk traps. Consequently, decreasing pre-existing bulk traps in I/O devices, which can be achieved by adopting HfxZr1−xO2 as gate oxide, can reduce the charge/discharge effect.

A novel method, called random telegraphy signal (RTS), was constructed to characterize the gate oxide quality and reliability of metal-oxide-semiconductor field-effect-transistors (MOSFETs). With the aggressive scaling of device size, drain current RTS (I D -RTS) become a critical role in carrier transport of MOSFETs. Besides, RTS in gate leakage current (I G -RTS) was denoted as the other new method to understand property of gate oxide. Recently, the study of RTS has also been made in MOSFETs with metal gate and high dielectric constant (metal gate/high-k). However, the RTS in partial depleted silicon-on-insulator MOSFETs (PD SOI MOSFETs) has not comprehensively been studied yet. This paper investigates RTS characteristics in PD SOI MOSFETs. IntroductionSilicon on insulator (SOI) MOSFETs have been attracted huge attention recently because of it lower power consumption, good soft-error immunity, increased circuit packing density and absence of CMOS latch-up (1-5). However, the self-heating effect (6-7) and floating body effect (FBE) (9) are the inherent disadvantages in SOI devices. In conventional FBE is attributed to the excess hole were generated by impact ionization in saturation region with floating body condition. The new FBE is in linear region, called gate-induced floating-body effect (GIFBE) due to the aggressive scaling gate oxide thickness induced by gate tunneling current (10-12, 25). Similarly, when device scale down to deep sub-micrometer the random telegraph noise (RTN) or so-called random telegraph signal (RTS) will be observed and influence device dynamic performance (8,22). The RTS phenomenon is commonly related to a carrier capture and emission behaviors. Recently, RTS has been considered as a major concern in scaling digital device because fluctuation of drain current amplitude (ΔI D ) will disturb analysis of signal (13-15). In the deep sub-micrometer MOSFETs device, it is possible to exist one or few oxide traps near the SiO2/Si interface which were distributed over the vicinity of Si surface Fermi level. These traps can be investigated by RTS (16). The high and low level states of drain current (I D ) vary randomly with time, which correspond to the carrier capture and emission at an oxide trap near the SiO2/Si interface. The average time at high level state of drain current corresponds to average capture time < τ c > which means how long will carrier be captured into the trap. On the other hand, the average time at low level state of drain current corresponds to average emission time < τ e > represent how