This paper presents a capacitor-less CMOS low dropout regulator (LDO) with a push-pull class AB amplifier, and a fast transient controller to achieve a better transient response. The undershoot/overshoot voltage and the settling time are effectively reduced. Through the theoretical analysis of the circuit, cadence simulation with SMIC 0.18μm process and under the condition of the input voltage range 1.4~4 V shows the output voltage is 1.2 V, with the fast controller the total quiescent current is 8.2 μA, the undershoot /overshoot voltage is 97 mV/47 mV and the settling time is 0.3 μs as load current suddenly changes from 1 to 100 mA, or vice versa. Compared with this paper without fast transient controller, the undershoot voltage, the overshoot voltage and the settling time are enhanced by 30%, 64% and 80%, respectively.

The objective of this paper is to provide tutorial treatment of the steps for analyzing poles and zeros in multi-stage amplifiers and low dropout (LDO) regulators. The steps can be easily all done by hand simplification without lacking for accuracy, and divided into two methods depending on whether Miller effect exists or not. A two-stage Simple Miller Compensation (SMC) amplifier and an output capacitor-less regulator are analyzed in detail, and several multi-stage amplifiers reported in the literature are also included. To this end, Cadence Spectre simulations are performed to compare hand-computed pole/zero locations with AC analysis.

This paper presents a bandgap reference and an output-capacitorless LDO regulator with adaptive power transistors. The bandgap reference consists of a current reference circuit, a bipolar transistor and proportional-to-absolute-temperature (PTAT) voltage generators. The proposed LDO improves load transient and light load efficiency by permitting the regulator to transform itself between 2-stage and 3-stage topologies, depending on the load current condition. Cadence simulation with SMIC 0.18 μm process shows that the bandgap reference generates a reference voltage 569 mV and the quiescent current is only 0.23 μA, the proposed LDO generates an output voltage 1 V, the quiescent current is 0.88 μA (including bandgap reference) at no-load condition, the undershoot /overshoot voltage is 187 mV/152 mV and the settling time is 5 μs as load current suddenly changes from 0 to 100 mA, or vice versa.

This paper proposes a new synchronized serial-parallel CRC(Cycle Redundancy Check) with PIE(Pulse Interval Encoding) decoding circuit for the UHF(Ultra-High Frequency) RFID(Radio Frequency Identification), which is based on the ISO/IEC 18000-6C standards protocol. The parallel algorithm of CRC circuit is derived, and the serial or parallel CRC circuit on RFID tag chip is evaluated in this paper. Finally, the designed circuit is simulated and analyzed on the FPGA platform. Simulation results show that the proposed circuit meets the communication requirement of the protocol and addresses the problem of low data processing rate of conventional serial CRC circuit, as well as implements 1 to 8 degree of parallelism of the parallel CRC circuit for UHF RFID.