A Liquid-argon Trigger Digitizer Board (LTDB) is being developed to upgrade the ATLAS Liquid Argon Calorimeter Phase-I trigger electronics. The LTDB located at the front end needs to obtain the clock signals and be configured and monitored remotely from the back end. A clock and control system is being developed for the LTDB and the major functions of the system have been evaluated. The design and evaluation of the clock and control system are presented in this paper.

In this paper, we present a dual-channel serializer ASIC, LOCx2, and its pincompatible backup, LOCx2-130, for detector front-end readout. LOCx2 is fabricated in a 0.25µm Silicon-on-Sapphire CMOS process and each channel operates at 5.12 Gbps, while LOCx2-130 is fabricated in a 130-nm bulk CMOS process and each channel operates at 4.8 Gbps. The power consumption and the transmission latency are 900 mW and 27 ns for LOCx2 and the corresponding simulation result of LOCx2-130 are 386 mW and 38 ns, respectively.

We present a wideband low-jitter LC-VCO phase-locked loop in 130 nm CMOS technology for high speed serial link applications. The PLL covers a 5.6 GHz to 13.4 GHz frequency range by using two LC-VCO cores with an RMS jitter of 370 fs. The single event effects testing is performed with a neutron beam at Los Alamos National Laboratory and no frequency disturbance is found over the test period. The PLL consumes 50.88 mW of power under a 1.2 V power supply.

In this paper, we present the design and test results of an encoder integrated circuit for the ATLAS Liquid Argon Calorimeter trigger upgrade. The encoder implements a low-latency and low-overhead line code called LOCic. The encoder operates at 320 MHz with a latency of no greater than 21 ns. The overhead of the encoder is 14.3%. The encoder is an important block of the transmitter ASIC LOCx2, which is prototyped with a commercial 0.25-µm Siliconon-Sapphire CMOS technology and packaged in a 100-pin QFN package.

A: This paper presents a 10-bit 250-MS/s time-interleaved pipelined analog-to-digital data converter (ADC). A distributed clocking scheme is developed to eliminate timing skew between channels without introducing load capacitance to the driving buffer of the ADC. The channel offset and gain mismatch errors are calibrated in digital domain. In addition, a switch-embedded opampsharing technique is developed to reduce the ADC power consumption and eliminate the memory effect. The simulated SNDR and SFDR are 61.84 dB and 78.2 dB, respectively. The ADC core consumes 28 mW under a 1.8 V supply at 250 MS/s sampling rate.