2015
DOI: 10.1088/1748-0221/10/03/c03013
|View full text |Cite
|
Sign up to set email alerts
|

A 12 GHz low-jitter LC-VCO PLL in 130 nm CMOS

Abstract: We present a wideband low-jitter LC-VCO phase-locked loop in 130 nm CMOS technology for high speed serial link applications. The PLL covers a 5.6 GHz to 13.4 GHz frequency range by using two LC-VCO cores with an RMS jitter of 370 fs. The single event effects testing is performed with a neutron beam at Los Alamos National Laboratory and no frequency disturbance is found over the test period. The PLL consumes 50.88 mW of power under a 1.2 V power supply.

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1
1

Citation Types

0
4
0

Year Published

2017
2017
2020
2020

Publication Types

Select...
3

Relationship

2
1

Authors

Journals

citations
Cited by 3 publications
(4 citation statements)
references
References 6 publications
0
4
0
Order By: Relevance
“…Since the tuning range of such a VCO is only about 10-15% of the central frequency, a series of capacitors parallel to the varactor are implemented in the VCO. The frequency of the VCO can be automatically adjusted by switching different capacitors [12]. The frequency adjustment process is implemented via the AFC module.…”
Section: Cdrmentioning
confidence: 99%
“…Since the tuning range of such a VCO is only about 10-15% of the central frequency, a series of capacitors parallel to the varactor are implemented in the VCO. The frequency of the VCO can be automatically adjusted by switching different capacitors [12]. The frequency adjustment process is implemented via the AFC module.…”
Section: Cdrmentioning
confidence: 99%
“…For example, during flooding or heavy rain, wires may become wet and thus provide poor signals, while wireless communication can be made to be more immune to water damage. As presented in Figure 8, the wireless communication hardware development can leverage our previous R&D works in which we have demonstrated a wideband cognitive radio transceiver and wireless channel emulator through a National Science Foundation (NSF)-funded project [10], a radiation-hard 6-12 GHz 00.37pS RMS jitter wideband LC-VCO phase-locked loop (PLL) [11], and radiationtolerant application specific integrated circuits (ASICs) for CERN's large hadron collider (LHC) detectors [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27]. In developing the wireless transceiver, commercial off-the-shelf (COTS) radiationhardened components based on Silicon-on-Sapphire (SOS) and Silicon on Insulator (SOI) technology should be utilized.…”
Section: Wireless Cnfa Sensormentioning
confidence: 99%
“…Figure 5 shows the die photo of the 0.13-µm CMOS PLL [7]. Measurements of the 0.13-µm PLL tuning characteristics at the divide-by-2 output show that the PLL covers a wide frequency range from 5.6 GHz to 13.4 GHz as shown in figure 6.…”
Section: Pllmentioning
confidence: 99%
“…A low jitter, radiation-tolerant and temperature-robust PLL is required to provide the clock signals for the serial link. The design of such a PLL presents several challenges [6][7][8]. First, as CMOS technology moves to smaller feature sizes and lower supply voltages, it becomes increasingly difficult to produce a low-jitter clock source.…”
Section: Phase-locked Loop and Clock Distributionmentioning
confidence: 99%