A low-power 12.5 Gbps serial link transmitter ASIC for particle detectors in 65 nm CMOS

Abstract

This paper presents a 12.5 Gbps serial link transmitter application-specific integrated circuit (ASIC) designed in a 65-nm CMOS technology. The ASIC mainly includes an LC-VCO phase-locked-loop (PLL), a 16:1 serializer and a CML driver. Simulation results show that the PLL achieves a 7-to-14 GHz frequency tuning range and an RMS jitter of 0.4 pS. The serializer has a deterministic jitter of 9 pS and a programmable output swing from 200 mV to 1.0 V. The PLL and the serializer consumes 39.6 mW and 73 mW from a 1.2 V power supply, respectively.

Carbon Nanofiber Aggregate Sensors for Sustaining Resilience of Civil Infrastructures to Multi-Hazards

“…For example, during flooding or heavy rain, wires may become wet and thus provide poor signals, while wireless communication can be made to be more immune to water damage. As presented in Figure 8, the wireless communication hardware development can leverage our previous R&D works in which we have demonstrated a wideband cognitive radio transceiver and wireless channel emulator through a National Science Foundation (NSF)-funded project [10], a radiation-hard 6-12 GHz 00.37pS RMS jitter wideband LC-VCO phase-locked loop (PLL) [11], and radiationtolerant application specific integrated circuits (ASICs) for CERN's large hadron collider (LHC) detectors [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27]. In developing the wireless transceiver, commercial off-the-shelf (COTS) radiationhardened components based on Silicon-on-Sapphire (SOS) and Silicon on Insulator (SOI) technology should be utilized.…”