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In this work, we demonstrate a two-step analysis procedure that enables an in-depth understanding of the localized charge trapping and charge decay mechanisms in metal nanocrystal (MNC)-embedded high-κ/SiO2 gate stacks. The results clearly reveal that vertical charge loss and lateral charge diffusion are two competing mechanisms, and they can be identified by discharging current measurements at elevated temperatures and the Kelvin force microscopy characterization. It is found that the MNC with higher work function has a lower inter-dot charge tunneling probability, which is favorable for improved retention in memory applications. However, the vertical charge loss during the initial decay period is a trade-off and it could be minimized by using a dual-layer MNC structure.

Abstract-Tri-level resistive switching behavior was observed in an Al 2 O 3 /SiO 2 gate stack with Ru metal nanocrystals embedded in the Al 2 O 3 layer. The device was successfully switched among three resistance states (high, medium, and low) after a forming process using a simple electrical method. The resistance ratio of the high-resistance state to the low-resistance state is more than 10 3 . The insulator-to-conductor (and vice versa) transition of the Al 2 O 3 and SiO 2 dielectric layers is elucidated by a physical model, which invokes oxygen ion (O 2− ) trapping/detrapping at the metal-oxide interfaces, as well as O 2− transport and annihilation with the oxygen vacancies in the breakdown percolation path. The switching transition of each individual dielectric layer is found to be dependent on the polarity of the gate bias. This new understanding opens the prospect of metal-nanocrystalbased Al 2 O 3 /SiO 2 gate stacks for a resistive switching memory application.Index Terms-Dielectric breakdown, metal nanocrystal (MNC), percolation path, resistive switching.

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In this work, we present a comprehensive experimental study of charge loss mechanisms in a dual-layer metal nanocrystal (DL-MNC) embedded high-j/SiO 2 gate stack. Kelvin force microscopy characterization reveals that the internal-electric-field assisted tunneling could be a dominant charge loss mechanism in DL devices that mainly depends on the charge distribution in two MNC-layers and inter-layer dielectric (ILD) thickness between the two layers of nanocrystals. Our findings suggest that an optimized DL-MNCs embedded memory cell could be achieved by defining the ILD thickness larger than the average MNC-spacing for enhancement of retention ability in MNC embedded gate stacks. It implies the possibility of reducing MNC spacing in DL structure of scaled memory devices by controlling the thickness of ILD. V