0.18 μm low voltage/low power RF CMOS with zero Vth analog MOSFETs made by undoped epitaxial channel technique

Abstract

We introduce 0.18 pn CMOS with multi-Vth's for mixed high-speed digital and FW-analog applications. The vth's of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are nMOSFETs with zero-volt-Vth for RF analog circuits. The zero-volt-Vth MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD), the film quality is good because higher pre-heating temperature (940 O C for 30 seconds) is used in H2 atmosphere before epitaxial growth. The epitaxial channel MOSFET shows higher peak &n and fT than those of bulk cases. Furthermore, the g,,, and fT values show significantly improved performances under the low supply voltage, which is important for 0.18 pm CMOS with low power 1 low supply voltage operation. Additionally, in our experiment no significant difference was observed between the reliability of gate oxide grown on bulk and the reliability of that grown on epitaxial layers. The undoped-epitaxial-channel MOSFETs with zero-Vth will be effective to realize high performance and low power CMOS devices for mixed digital and RF-analog applications.

The Effect of Technology Scaling on Power Dissipation in Analog Circuits

“…The above equation shows a very weak dependence on distortion and signal swing and strong dependence on signal frequency, load capacitance and transistor biasing (V gt ). Comparing this result to Bandwidth dominated situations (equation (26)) reveals that settling to an absolute accuracy is a more stringent requirement than achieving a certain Bandwidth. The ratio between the two requirements is:…”

“…( 2 7 ) Comparing to (26) shows that, usually, the minimum current to prevent Slewing is larger than the current required for a certain Bandwidth. However, the two requirements become equal for:…”

“…Use of low-V th devices may be a solution [26,27], but at higher cost. Several different clock-boosting techniques [28][29][30][31] have been proposed, though the necessary circuitry is fairly complicated and use of those techniques is usually limited to just a few critical switches.…”

“…10 shows all previously discussed bias-currents as a function of the Technology (L min ). The equations used to generate these curves are (26), (27), (32), (33), (37), (38), (42) and (48). To determine the absolute positions of the curves, the design parameters listed in Table 1 have been used.…”

“…6) may endanger that assumption. Several papers [26][27][28][29][30][31][32][33][34][35][36][37][38][39][40]52] have been published addressing this problem. Two of the most severe problems are Switches and OpAmps.…”