0.75-V four-quadrant current multiplier using floating gate-MOS transistors

Abstract

This paper presents a new ultra-low-voltage current-mode four-quadrant analog multiplier. A floating-gate technique is used to provide operating at a supply voltage of 0.75 V for the proposed circuit. PSPICE simulators using 0.18 /lm TSMC CMOS process are used to show the workability of the multiplier. Simulation results show that the circuit has a linearity error of 1.5 % for the input current 8 /lA, total harmonic distortion of 0.96 % for the input current 8 /lApe ak and quiescent power consumption of 19.9 /lW.

The CMOS Highly Linear Current Amplifier with Current Controlled Gain for Sensor Measurement Applications

“…The current-mode multipliers are important for our discussion due to similarity of newly proposed concept also using principle of two-quadrant multiplier. Comprehensive comparison [ 28 , 29 , 30 , 31 , 32 , 33 , 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 53 , 54 , 55 , 56 , 57 , 58 , 59 , 60 , 61 , 62 , 63 , 64 , 65 , 66 , 67 , 68 ] in Table 2 indicates missing details and incomplete topologies for full implementation in current multiplication or amplification because structures are not designed as fully symmetrical form. They operate with intentional superposition of DC component or principal topology, not including all important parts, in order to obtain behavior required in this work.…”