1/f noise suppression of pMOSFETs fabricated on Si(100) and Si(110) using an alkali-free cleaning process

Gaubert, Philippe; Teramoto, Akinobu; Hamada, T.; Yamamoto, Masashi; Kotani, Kazuhiko; Ohmi, Tadahiro

doi:10.1109/ted.2006.871188

Cited by 47 publications

(32 citation statements)

References 12 publications

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“…It is found that the obtained 1/f noise level is close to that of the MOSFET with SiO 2 gate insulator fabricated on the atomically flat Si(100) substrate indicated by the dashed line in Fig. 9(a) [41]. This result suggested that the flattening Fig.…”

Section: Introductionsupporting

confidence: 61%

Importance of Si surface flatness to realize high-performance Si devices utilizing ultrathin films with new material system

Ohmi

2014

IEICE Electron. Express

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The importance of Si surface flatness on metal-oxide-semiconductor field-effect transistor (MOSFET) characteristics with ultrathin hafnium oxynitride (HfON) high-k gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering was described. The surface roughness of Si substrate was reduced by Ar/4.9%H 2 annealing utilizing conventional rapid thermal annealing (RTA) system. Si surface root-mean-square (RMS) roughness was well controlled by changing the annealing temperature from 700 to 1000°C. Si surface RMS roughness after 1000°C/1 hr annealing was 0.078 nm for Si(100) and 0.082 nm for Si(110), respectively. Clear dependence of electrical characteristics of MOS diodes such as equivalent oxide thickness (EOT) and leakage current on the surface RMS roughness of Si(100) and Si(110) was observed, and the electrical characteristics were remarkably improved by decreasing of surface RMS roughness. The MOSFET characteristics with HfON gate insulator fabricated on Si(100) substrates after flattening process were also improved.

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Section: Introductionsupporting

confidence: 61%

Importance of Si surface flatness to realize high-performance Si devices utilizing ultrathin films with new material system

Ohmi

2014

IEICE Electron. Express

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“…In particular, it is essential to fabricate a gate insulator with a level of defect as low as possible 11 as well as an interface semiconductor/insulator as flat as possible. 12,13 As a consequence, the quality of processes involved in the fabrication of the gate insulator can be characterized by the evaluation of the low frequency noise. [14][15][16] Some are explaining the 1 / f noise through a bulk phenomenon induced by the fluctuation of mobility in the lattice, 17 first introduced during the 1970s by Hooge and generally noted ⌬, while others are attributing it to a fluctuation in the number of carriers caused by interface traps, 18,19 this model is the McWhorter one, generally abbreviated ⌬N.…”

Section: Introductionmentioning

confidence: 99%

Different mechanism to explain the 1∕f noise in n- and p-SOI-MOS transistors fabricated on (110) and (100) silicon-oriented wafers

Gaubert

Teramoto

Cheng

et al. 2009

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Articles you may be interested inAging mechanism of the native oxide on silicon (100) following atmospheric oxygen plasma cleaning J. Vac. Sci. Technol. A 29, 041403 (2011); 10.1116/1.3597436 Channel direction, effective field, and temperature dependencies of hole mobility in (110)-oriented Ge-oninsulator p-channel metal-oxide-semiconductor field-effect transistors fabricated by Ge condensation technique J. Appl. Phys. 109, 033709 (2011); 10.1063/1.3537919Influence of uniaxial mechanical stress on the high frequency performance of metal-oxide-semiconductor field effect transistors on (100) Si wafer Appl.

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“…It is well known that roughness at silicon/gate insulator interface degrades the MOS inversion layer mobility by scattering mechanism caused by the roughness [1,2]. Also, some papers report on the impact of the flatness of the interface on 1/f noise characteristics [3,4]. Then, a recent work has proposed that the MOS inversion layer mobility and current drivability of MOSFETs can be improved by the introduction of atomically flat gate insulator/silicon interface up to very high speed performance [5].…”

Section: Introductionmentioning

confidence: 99%

Atomically flat gate insulator/silicon (100) interface formation introducing high mobility, ultra-low noise, and small characteristics variation CMOSFET

Kuroda

Teramoto

Suwa

et al. 2008

ESSDERC 2008 - 38th European Solid-State Device Research Conference

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Atomically flat silicon surface constructed with atomic terraces and steps is realized by pure argon ambience annealing at 1200 o C on (100) crystal orientation large diameter wafers with precisely controlled tilt angle. Only the radical reaction based insulator formation technology such as oxidation utilizing oxygen radicals carried out at low temperature (400 o C) can preserve the atomically flatness at the gate insulator film/silicon interface. CMOSFET having the atomically flat interface exhibit extremely lower 1/f noise and higher mobility characteristics with smaller electrical variation than those of CMOSFETs fabricated by the conventional technologies.

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1/f noise suppression of pMOSFETs fabricated on Si(100) and Si(110) using an alkali-free cleaning process

Cited by 47 publications

References 12 publications

Importance of Si surface flatness to realize high-performance Si devices utilizing ultrathin films with new material system

Importance of Si surface flatness to realize high-performance Si devices utilizing ultrathin films with new material system

Different mechanism to explain the 1∕f noise in n- and p-SOI-MOS transistors fabricated on (110) and (100) silicon-oriented wafers

Atomically flat gate insulator/silicon (100) interface formation introducing high mobility, ultra-low noise, and small characteristics variation CMOSFET

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