Atomically flat gate insulator/silicon (100) interface formation introducing high mobility, ultra-low noise, and small characteristics variation CMOSFET

Abstract

Atomically flat silicon surface constructed with atomic terraces and steps is realized by pure argon ambience annealing at 1200 o C on (100) crystal orientation large diameter wafers with precisely controlled tilt angle. Only the radical reaction based insulator formation technology such as oxidation utilizing oxygen radicals carried out at low temperature (400 o C) can preserve the atomically flatness at the gate insulator film/silicon interface. CMOSFET having the atomically flat interface exhibit extremely lower 1/f noise and higher mobility characteristics with smaller electrical variation than those of CMOSFETs fabricated by the conventional technologies.

Carrier mobility characteristics of (100), (110), and (551) oriented atomically flattened Si surfaces for fin structure design of multi-gate metal–insulator–silicon field-effect transistors

“…However, almost no increase was observed for E eff larger than 0.8 MV/cm. 8) The impact of interface flatness to the electron mobility has been experimentally confirmed at high E eff region when the roughness level is relatively large such as R a ranging from 0.2 to 1.5 nm. 7,29,30) The experimental results obtained in this work shows that the electron mobility is less sensitive to the flatness under the atomic scale flatness level at high E eff region and actually more sensitive at relatively low E eff region.…”

“…For hole mobility, an unique temperature point was found at around 180 K where the E eff dependency of mobility increase crosses over. 8) It should be noted that at the high E eff region, the improvement of the hole mobility is larger than that for electron mobility. This result indicates that the hole mobility is more sensitive to the flatness than that of electron at the atomic scale flatness level.…”

“…[3][4][5][6] The Si surface orientation and its flatness are ones of the determinant factors that gratefully impact the carrier mobility. [3][4][5][6][7][8] Due to its high immunity to the short channel effect, multi-gate metal-insulator-silicon FETs (MuGFETs) are now replacing the planar MOSFETs at the 22 nm node and beyond. [9][10][11] There is variety of MuGFETs' fin structures reported in the literatures up to date.…”

Evaluation of Low-Frequency Noise in MOSFETs Used as a Key Component in Semiconductor Memory Devices

“…The interface roughness degrades not only electron mobility [66][67][68][69][70][71] and gate dielectric reliability [72][73][74], but also noise generation [71,75,76]. An atomically flat interface [77][78][79][80][81][82][83][84] is effective for reducing low-frequency noise [79,[83][84][85][86][87].…”

Impact of Channel Direction Dependent Low Field Hole Mobility on (100) Orientation Silicon Surface

“…[6][7][8][9] Also, an introduction of (110) orientation surface as well as, the improvement of flatness between gate insulator film/silicon interface have been studied to increase the relaxation time constant of lattice phonon scattering for holes and interface roughness scattering for both electrons and holes, respectively. [10][11][12][13] It is well known that the heavy hole effective mass has a direction dependency. 14) Sayama et al reported on the improved current drivability of p-channel MOSFET (pMOS) on (100) surface along the [001] channel direction instead of the conventional [011] channel direction.…”