10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores

Igarashi, M.; Uemura, Tomomasa; Mori, Ryota; Maeda, Noriaki; Kishibe, Hiroshi; Nagayama, Midori; Taniguchi, Masateru; Wakahara, Kohei; Saito, T.; Fujigaya, Masaki; Fukuoka, Kazuki; Nii, Koji; Kataoka, Takeshi; Hattori, Toshihiro

doi:10.1109/isscc.2014.6757389

Cited by 5 publications

(3 citation statements)

References 5 publications

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“…Each of these architectures exploit characteristics of benchmarks such as data-level parallelism, pipelined data flow, specialized memory access patterns to improve performance and energy savings. Heterogeneous SMP:The 28nm Renesas electronics quad/octa core mobile application processor [18], ARM big.LITTLE platform, Nvidia Tegra propose combining high performance cores and low power cores with adaptive voltage scaling techniques. Media Tek 28nm heterogeneous mobile processor [32] consisting of ARM Cortex A15 and A7 cores includes several power, thermal and performance optimizations.…”

Section: Related Workmentioning

confidence: 99%

Exploring architectural heterogeneity in intelligent vision systems

Chandramoorthy

Tagliavini

Irick

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

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Limited power budgets and the need for high performance computing have led to platform customization with a number of accelerators integrated with CMPs. In order to study customized architectures, we model four customization design points and compare their performance and energy across a number of computer vision workloads. We analyze the limitations of generic architectures and quantify the costs of increasing customization using these micro-architectural design points. This analysis leads us to develop a framework consisting of low-power multi-cores and an array of configurable micro-accelerator functional units. Using this platform, we illustrate data flow and control processing optimizations that provide for performance gains similar to custom ASICs for a wide range of vision benchmarks.

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Section: Related Workmentioning

confidence: 99%

Exploring architectural heterogeneity in intelligent vision systems

Chandramoorthy

Tagliavini

Irick

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

View full text Add to dashboard Cite

show abstract

“…However, the improvement is negligible and cannot sustain couple of cycles of voltage drop. Reference [4] proposed a methodology to…”

Section: Distributed On-chip Voltage Compensatormentioning

confidence: 99%

Design of near-threshold microcontroller for wireless sensing applications

Tang

Lin

Haung

2015

VLSI Design, Automation and Test(VLSI-Dat)

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This paper reveals an in-house microcontroller, BLAZE, running at 1MHz and 0.4V. In order to deploy BLAZE under strict environments, an on-chip distributed voltage compensator is proposed. With these compensators whose layout size are similar to standard DECAP cell, the voltage stability improves more than 20.3% compared to DECAP cells. To reduce the extra power source and level-shifter a single voltage IO cell is proposed with less than 28% performance degradation. BLAZE is also evaluated for wireless sensing applications, and the results show that BLAZE is more suitable to work under near-threshold regime than race-to-sleep.

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“…In the aspect of circuits, most dynamic thermal management schemes, such as the clock gating technique, power gating, and sleep transistor insertion techniques, are often implemented in low-power design to alleviate the thermal issue [4]. By decreasing frequency and voltage, even powering OFF some functional units to reduce the on-die junction temperature, a thermal throttling sensor was calibrated to keep the operating temperature within the specified range [5]. However, these techniques were carried out at the cost of extra area, performance, and sensor noise penalty.…”

Section: Introductionmentioning

confidence: 99%

Improvement of Thermal Environment by Thermoelectric Coolers and Numerical Optimization of Thermal Performance

Wang

Mao

2015

IEEE Trans. Electron Devices

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Seeking for an available thermal runaway solution is becoming one important and challenging issue in current nanometer ICs. Thermoelectric coolers (TECs) may give a solution. In this paper, a simplified power model of circuits closely associated with temperature with and without repeaters is derived. Based on the surface temperature difference and heat-flow density, an equivalent thermal resistance model for powered TECs is proposed. According to the thermal profile model, the steady-state temperature is calculated for the same chip with two different package forms. Finally, optimizations of p-n couples are performed with the purpose of obtaining the maximum coefficient of performance (COP) and minimum TECs power. As compared with the traditional flip-flop controlled-collapse-chip-connection package, the results reveal desirable conclusions that a 15.8% decrease of the chip stability temperature with the COP optimization at I = 2.5 A and 11.4% steady-state power savings with the 13.2 W TEC power consumption are obtained in a 50-nm technology node. Analysis demonstrates that the maximum COP and minimum power consumed by TECs can be obtained at different optimum numbers of p-n couples, which is independent of electrical current across by TECs.

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10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores

Cited by 5 publications

References 5 publications

Exploring architectural heterogeneity in intelligent vision systems

Exploring architectural heterogeneity in intelligent vision systems

Design of near-threshold microcontroller for wireless sensing applications

Improvement of Thermal Environment by Thermoelectric Coolers and Numerical Optimization of Thermal Performance

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