16 Mbit SRAM cell technologies for 2.0 V operation

Abstract

New memory cell technologies for 2.0V cell operation of 16Mbit SRAMs have been developed. These technologies have realized 7.2p.m' cell size, 4.4 effective cell ratio for high noise immunity and l&nA/cell leakage current. The key features of these technologies include; 1) a symmetrical cell configuration, 2) an access transistor with N-offset resistor, 3) a ground plate expanded on the cell area, and 4) a poly Si TFT(Thin Film Transistor) with an LDO(Light1y Doped Offset) structure, all of which are based on a 0.4pm design rule using a SAC(Self Aligned Contact) process. The access transistor with an N-offset resistor increases the cell ratio without expanding cell size. The symmetrical cell configuration, the ground plate and the TFT with the LDO structure contribute to cell operation stability.

High performance 0.25 μm SRAM technology with tungsten interpoly plug

“…The severe trade-off between onand off-currents is met with separate optimization of memory and logic NMOS FETs [2]. Low voltage bitcell operation was studied using circuit simulation and was improved by avoiding the P/N poly diode between the PMOS TFT and NMOS latch transistor with a tungsten interpoly plug and by using an LDD resistor [3] to improve bitcell stability. With lower voltages and smaller cells, less charge is stored and soft error becomes critical, forcing use of a stacked capacitor and a triple well structure [4].…”