2-Bit-Per-Cell RRAM-Based In-Memory Computing for Area-/Energy-Efficient Deep Learning

He, Wangxin; Yin, Shihui; Kim, Yulhwa; Sun, Xiaoyu; Kim, Jae‐Joon; Yu, Shimeng; Seo, Jae-sun

doi:10.1109/lssc.2020.3010795

Cited by 48 publications

(30 citation statements)

References 9 publications

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“… Peng et al (2019 ). The simulation is set up across versatile device technologies (HfOx RRAM ( He et al, 2020 ), TaOx/HfOx RRAM ( Wu et al, 2018 ), PCM ( Kim et al, 2019 ), and FeFET ( Ni et al, 2018 ), as shown in Table 7 . SRAM-based CIM accelerators are evaluated at both 22 and 7 nm, and eNVM-based ones are evaluated at 22 nm as 22 nm is the state-of-the-art node where the eNVMs are integrated.…”

Section: Benchmarkmentioning

confidence: 99%

“…SRAM-based CIM accelerators are evaluated at both 22 and 7 nm, and eNVM-based ones are evaluated at 22 nm as 22 nm is the state-of-the-art node where the eNVMs are integrated. Considering the read-noise and on/off ratio, the 4-bit/cell is assumed for eNVMs, except the 2-bit RRAM from Winbond ( He et al, 2020 ). The subarray size is 128 × 128.…”

Section: Benchmarkmentioning

confidence: 99%

“…To our best knowledge, none of other CIM simulators have been validated with the actual silicon data, although the peripheral circuit modules (e.g., decoder, switch matrix, mux, and adder) of NeuroSim have been validated with SPICE simulations using the PTM model (PTM, 2011) and FreePDK (FreePDK, 2014). It is known that the PTM model and FreePDK are for educational purposes, rather than for foundry fabrication purposes.…”

Section: Introductionmentioning

confidence: 99%

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NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark

Peng

et al. 2021

Front. Artif. Intell.

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Compute-in-memory (CIM) is an attractive solution to process the extensive workloads of multiply-and-accumulate (MAC) operations in deep neural network (DNN) hardware accelerators. A simulator with options of various mainstream and emerging memory technologies, architectures, and networks can be a great convenience for fast early-stage design space exploration of CIM hardware accelerators. DNN+NeuroSim is an integrated benchmark framework supporting flexible and hierarchical CIM array design options from a device level, to a circuit level and up to an algorithm level. In this study, we validate and calibrate the prediction of NeuroSim against a 40-nm RRAM-based CIM macro post-layout simulations. First, the parameters of a memory device and CMOS transistor are extracted from the foundry’s process design kit (PDK) and employed in the NeuroSim settings; the peripheral modules and operating dataflow are also configured to be the same as the actual chip implementation. Next, the area, critical path, and energy consumption values from the SPICE simulations at the module level are compared with those from NeuroSim. Some adjustment factors are introduced to account for transistor sizing and wiring area in the layout, gate switching activity, post-layout performance drop, etc. We show that the prediction from NeuroSim is precise with chip-level error under 1% after the calibration. Finally, the system-level performance benchmark is conducted with various device technologies and compared with the results before the validation. The general conclusions stay the same after the validation, but the performance degrades slightly due to the post-layout calibration.

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Section: Benchmarkmentioning

confidence: 99%

Section: Benchmarkmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark

Peng

et al. 2021

Front. Artif. Intell.

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“…CIM accelerators based on the mainstream device technologies such as SRAM [3][4], NOR Flash [5] and NAND Flash [6][7][8][9] have been proposed and verified in silicon. Furthermore, the emerging nonvolatile (NVM) memories such as RRAM [10][11][12][13][14][15] and PCM [16][17] have been considered as strong candidates due to the multilevel capability (over SRAM) and lower programming voltage (over Flash).…”

Section: Introductionmentioning

confidence: 99%

Ferroelectric Field-Effect Transistor-Based 3-D NAND Architecture for Energy-Efficient on-Chip Training Accelerator

Shim

2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Different from the deep neural network (DNN) inference process, the training process produces huge amount of intermediate data to compute the new weights of the network. Generally, on-chip global buffer (e.g. SRAM cache) has limited capacity because of its low memory density, therefore the off-chip DRAM access is inevitable during the training sequences. In this work, a novel ferroelectric field effect transistor (FeFET) based 3D NAND architecture for on-chip training accelerator is proposed. The reduced peripheral circuit overheads owing to the low operation voltage of FeFET device and ultra-high density of 3D NAND architecture enables storing and computing all the intermediate data on chip during the training process. We present a custom design of 108 Gb chip with 59.91 mm 2 area with 45 % array efficiency. The relevant data mapping schemes for weights/activations/errors that are compatible to the 3D NAND architecture are investigated. The training performance was explored while ResNet-18 model is trained on this architecture with ImageNet dataset by 8-bit precision. Thanks to the minimized off-chip memory access, 7.76 TOPS/W of energy efficiency was achieved for 8-bit on-chip training.

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“…The input vector will activate multiple rows of memory through voltage, the current along the columns will represent the weighted sum output vector [2]. CIM prototypes of static random-access memory (SRAM) [3,4] and emerging non-volatile memories (eNVMs) such as phase change memory (PCM) [5,6] and resistive random access memory (RRAM) [7][8][9] have been demonstrated in silicon.…”

Section: Introductionmentioning

confidence: 99%

Cryogenic Performance for Compute-in-Memory Based Deep Neural Network Accelerator

Wang

Peng

Chakraborty

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Compute-in-memory has received a lot of research interests recently to implement the data-intensive computation in deep neural networks. By performing the computing at the storage location, CIM avoids the excessive data transfer thus improving the energy efficiency. SRAM based CIM is one of the promising candidates for its mature technology availability at advanced technology node. To further speed up for CMOS circuits, cryogenic computing which operates at low temperatures has emerged as an attractive solution for highperformance computing at the data center. In this work, we modified NeuroSim, a device-to-system modelling framework with experimentally calibrated 28nm transistor parameters from room temperature to 4K. Then we benchmark the performance of SRAM based CIM for ResNet-18 on ImagNet dataset. The energy-delay-product is compared across the temperature, revealing the performance and energy efficiency boost by cryogenic computing. When the cooling infrastructure cost is considered, the overall energy benefits are overshadowed though.

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2-Bit-Per-Cell RRAM-Based In-Memory Computing for Area-/Energy-Efficient Deep Learning

Cited by 48 publications

References 9 publications

NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark

NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark

Ferroelectric Field-Effect Transistor-Based 3-D NAND Architecture for Energy-Efficient on-Chip Training Accelerator

Cryogenic Performance for Compute-in-Memory Based Deep Neural Network Accelerator

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