2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology

Somasekhar, Dinesh; Ye, Yibin; Aseron, Paolo; Lu, Shih-Lien; Khellah, Muhammad; Howard, Jason D.; Ruhl, G.; Karnik, Tanay; Borkar, S.; De, Vivek; Keshavarzi, Ali

doi:10.1109/jssc.2008.2007155

Cited by 71 publications

(49 citation statements)

References 7 publications

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“…The 2T DRAM cell shown in Figure 11(a) is derived from the well known 3T-DRAM and was proposed recently as a potential memory cell for microprocessor's cache [9]. The main advantage of this memory cell is that it uses a full CMOS technology and it improves density compared to the 3T-DRAM, by removing the access transistor.…”

Section: T Dram Implementationmentioning

confidence: 99%

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A Compact Digital Pixel Sensor (DPS) Using 2T-DRAM

Zhang

Leomant

Lau

et al. 2011

JLPEA

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Abstract:In digital pixel sensors (DPS), memory elements typically occupy large silicon area of the pixel, which significantly reduces the pixel's fill factor while increases its size, power and cost. In this work, we propose to reduce DPS memory's area and power overhead by reducing the memory requirements with a multi-reset integration scheme, and meanwhile employing a dynamic memory instead of traditionally exploited large 6T-SRAM cell. The operation of the DPS takes advantage from the chronological change of the code, which results in reduced memory needs without affecting the light resolution. In the proposed implementation, a 4-bit in-pixel memory is used to reduce the pixel size, and an 8-bit resolution is achieved with multi-reset scheme. In addition, full complementary metal-oxide-semiconductor (CMOS) 2T DRAM and selective refresh scheme are adopted to implement the memory elements and further increase the area savings. This paper presents the proposed multi-reset integration methodology and its implementation with dedicated memory circuits. Proposed architecture is validated by a prototype chip fabricated using AMS 0.35 µm CMOS technology. Reported experimental results are compared with relative works.

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Section: T Dram Implementationmentioning

confidence: 99%

“…As the sensing operation is differential, the generation of a reference voltage is required. The reference voltage is generated as in [9]. The transposed bit-line architecture allows to reduce the coupling effects between two adjacent lines but adds some complexity.…”

Section: Read and Refresh Circuitmentioning

confidence: 99%

A Compact Digital Pixel Sensor (DPS) Using 2T-DRAM

Zhang

Leomant

Lau

et al. 2011

JLPEA

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“…One of the interesting alternative implementations that addresses these limitations, while continuing to provide full CMOS logic compatibility, is gaincell (GC) embedded DRAM (eDRAM), such as the circuit illustrated in Fig. 1(a) [2]- [5]. Most often consisting of two (2T) or three (3T) transistors, GC-eDRAMs provide a reduced silicon footprint, along with inherent 2-port functionality, nonratioed circuit operation, and very low static leakage currents from V DD to GND.…”

Section: Introductionmentioning

confidence: 99%

“…As this undesired coupling even increases with WWL boost magnitude, a clear tradeoff between write speed, power, and DRT is introduced [5]. In addition, the levelshifting and toleration of higher than nominal voltages can be complex, especially when this boosted voltage is a negative underdrive voltage, as required by implementations employing a PMOS write transistor [2], [4]. The propagation of such a negative voltage can easily lead to voltage drops over device terminals that violate the technology limitations.…”

Section: Introductionmentioning

confidence: 99%

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

Giterman

Teman

Meinerzhagen

et al. 2016

IEEE Trans. VLSI Syst.

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Abstract-Logic compatible gain cell (GC) embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, non-ratioed operation, low static leakage, and 2-port functionality. However, traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. These boosted levels require either an extra power supply or on-chip charge pumps, as well as non-trivial level shifting and toleration of high voltage levels. In this paper, we present a novel, logic compatible, 3T GC-eDRAM bitcell that operates with a single supply voltage and provides superior write capability to conventional GC structures. The proposed circuit is demonstrated with a 2 kb memory macro that was designed and fabricated in a mature 0.18 µm CMOS process, targeted at low-power, energyefficient applications. The test array is powered with a single supply of 900 mV, showing an 0.8 ms worst-case retention time, a 1.3 ns write-access time, and 2.4 pW/bit of retention power. The proposed topology provides a bitcell area reduction of 43%, as compared to a redrawn 6T SRAM in the same technology, and an overall macro area reduction of 67% including peripherals.

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“…The gain cell in a hybrid structure of PMOS and NMOS [8] also consumes a spacious bit-area because of large well-towell space. The 2T structure in a same type of transistors would provide most compact bit-area, but the all-PMOS 2T cells [9][10][11] may limit the read performance of the memory due to the poor channel mobility of PMOS read device.…”

Section: Introductionmentioning

confidence: 99%