3.3V-5V compatible I/O circuit without thick gate oxide

Takahash, M.; Sakurai, Takayasu; Sawada, Katsutoshi; Nogami, K.; Ichida, M.; Matsuda, K.

doi:10.1109/cicc.1992.591341

Cited by 27 publications

(13 citation statements)

References 4 publications

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“…Besides, the PMOS devices in stacked configuration occupy more silicon area. In case of the mixedvoltage I/O buffer with a depletion PMOS device as discussed in [3] uses an extra pad that is connected to 3.3-V power supply (VDDH).However, using the depletion device increases mask layer and process modification. Thus, the fabrication cost of such I/O buffer design will be increased.…”

Section: A Prior Designsmentioning

confidence: 98%

“…In the earlier designs as discussed in [1], [2], [3], [4] because the floating n-well is clamped to 2.5Vor 3.3V through the parasitic diodes by some dynamic n-well bias circuits the voltage on the floating n-well will be a little lower than 2.5 V or 3.3 V. The lower floating n-well voltage results in the lower threshold voltage of the pull-up PMOS transistor. Thus, the subthreshold leakage current becomes large when the pull-up PMOS transistor is in off state.…”

Section: A Prior Designsmentioning

confidence: 99%

“….The pull-up protection circuit consist of transistor T33 which switch the gate voltage of T34 to pad voltage when 3.3volts appear at the pad. 1.7ns Design [3] 1.6ns Design [4] 1.63ns Design [6] 1.54ns Proposed Design 1.3ns [1] 17mW Design [2] 16.6mW Design [3] 13.8mW Design [4] 12.6mW Design [6] 11.3mW Proposed Design 8mW…”

Section: Description Of Proposed Circuitmentioning

confidence: 99%

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Simplified 3.3V tolerance circuit for 2.5V I/O design in PCI-X signaling environment

Salimath

Mandavilli

2009

2009 52nd IEEE International Midwest Symposium on Circuits and Systems

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A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. The interface circuit includes an impedance control circuit, an output buffer, an input buffer, an isolation circuit and a pull up protection circuit. When a high voltage is applied to the IO pad ,the pull-up protection circuit drives the gate of the pull up transistor to the high IO pad voltage to ensure that no current flows to the positive supply voltage. Also the isolation circuit couples the high IO pad voltage to the body of the pull-up transistor to prevent leakage current through parasitic diodes formed by the pull-up transistor.

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Section: A Prior Designsmentioning

confidence: 98%

Section: A Prior Designsmentioning

confidence: 99%

Section: Description Of Proposed Circuitmentioning

confidence: 99%

See 1 more Smart Citation

Simplified 3.3V tolerance circuit for 2.5V I/O design in PCI-X signaling environment

Salimath

Mandavilli

2009

2009 52nd IEEE International Midwest Symposium on Circuits and Systems

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“…While the latter is fully compatible with standard integration processes, the former is restricted to fabrication processes featuring such a sort of device, although several design techniques relying on DM P-MOSFETs have been reported, e.g. [10][11][12][13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

A current limiter for DC/DC regulators with compensation against process and temperature variations

Lima

Pimenta

2009

Analog Integr Circ Sig Process

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A low-voltage current limiter suitable for both linear and switching regulators is presented. Although the approach relies on absolute values of sense resistance and MOSFET threshold voltage on subsequent I/V and V/I conversions of the sensed current, a reference current in the process and temperature (PT) compensator is derived in such a manner that the dependence of clamping threshold I TH on PT-spread is first-order canceled out. Furthermore, the current sensor embodies a transconductor build up with either p-MOSFET depletion-mode device or a level-shifter with enhancement-mode transistors, meeting low-dropout requirements. For nominal value of 750 mA, Monte Carlo data express boundaries for I TH of 523 and 1,075 mA, accounting for broad PT-variation, as well as operating voltages and mismatching. A linear regulator with 400 mA-current rate and 250 mV-dropout incorporating the limiter on its depletion p-MOSFET version was integrated on a smart-power process. The limiter occupies an area of 0.052 mm 2 and consumes only 65 lA. Experimental data attest the clamper functionality and accuracy against PT-variations. From samples of distinct lots, I TH spans from 615 to 996 mA. Owing to its simplicity and open-loop operation in case of switchers, the limiter reacts upon overcurrent in only 20 ns, making it compatible with converters functioning in MHz range and under low dutycycles. Moreover, the limiter suits supply voltages as low as 1 V.

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“…To solve the gate-oxide reliability issue without using the additional thick gate oxide process (also known as dual gate oxides in some CMOS processes [5], [6]), the stacked-MOS configuration has been widely used in the mixed-voltage I/O buffers [7]- [12], and in the power-rail ESD clamp circuits [13]. The typical 3-V/5-V-tolerant mixed-voltage I/O circuit is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%