Bending vibration of flexible structures can be suppressed passively using piezoelectric electromechanical transducers and optimally tuned LR circuits. Since these systems include both mechanical and electrical elements, the governing equations consist of electrically coupled equations of motion. This paper describes a new method for deriving the governing equations that describe a system's vibration suppression based on the equilibrium of force principle and using an equivalent mechanical model of a piezoelectric element. Both series and parallel LR circuits are considered in the modeling approach. The optimum values for a mechanical vibration absorber can be formulated by using the two fixed points method. However, exact optimal values for the resistances of the LR circuits have not been formulated in the research literature thus far, and approximate values have been used. Analytical formulations are derived in this paper, and optimum values of the LR circuits are presented, not only in displacement, but also in terms of velocity and acceleration. The effects of the stiffness of the adhesive bond between the host structure and piezoelectric element, the dielectric loss in a piezoelectric element, and the internal resistance of an inductor are considered in the theoretical analysis. The effectiveness of the described analytical method is validated through simulations and experiments.

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Manufacturing of integrated circuits relies on the sequence of many hundred process steps. Each of these steps will have more or less variation, wbicb has to be within a certain limit to guarantee the chips functionality at a target speed. But, not every chip layout is susceptive to process variation the same way, wbicb requires a link between process capabilities and product design. This paper will present a novel Logic Characterization Vehicle (LCV) to investigate the yield and performance impact of process variation on high volume product chips. The LCV combines and manipulates new or already documented circuits like memory cells and combinatorial logic circuits within a JIG interface that allows fast and easy testability. Beside the functionality of such circuits, also path delay as well as cross talk issues can be determined. A standard digital functional tester can be used, since all timing critical measurements will be performed within the JIG. The described method allows early implementation of existing circuits for future technology nodes (shrinks). A Design Of Experiments (DOE) based implementation of possible layout manipulations will determine their impact on yield and performance of a target design as well as its sensitivity to process variation. The described approach can be used at a much earlier stage of product and process development, which will significantly shorten yield ramp.