30.5 A 0.5V BLE Transceiver with a 1.9mW RX Achieving −96.4dBm Sensitivity and 4.1dB Adjacent Channel Rejection at 1MHz Offset in 22nm FDSOI

Tamura, Masamitsu; Takano, Hideyuki; Shinke, Satoru; Fujita, Hiroaki; Nakahara, Hironori; Suzuki, Norihito; Nakada, Yutaka; Shinohe, Yusuke; Etou, Shinichirou; Fujiwara, T.; Katayama, Yasushi

doi:10.1109/isscc19947.2020.9063021

Cited by 26 publications

(12 citation statements)

References 6 publications

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“…Onethird of the area of our prior implementation of the type-II PT-RX [1] has been saved thanks to the inductor-free LNTA architecture as well as the bandwidth optimization of DT LPF. Compared to the Cartesian RXs in [5], [8], at least 2× better area utilization has been achieved due to the removed quadrature down-conversion path.…”

Section: Resultsmentioning

confidence: 99%

“…By substituting formula (11) into ( 9) and assuming Taylor series expansion, 5 the PD controller output is derived as follows,…”

Section: B Loop Delay Optimizationmentioning

confidence: 99%

“…W ITH the increasingly high demand for Internet-of-Things (IoT) devices, there is a strong push for ultralow power (ULP) and ultra-low voltage (ULV) operation of wireless nodes [1]- [6]. The conventional in-phase/quadrature (I/Q) or Cartesian receivers (RX) still dissipate large amounts of power, e.g., >5 mW for commercial products [7] and >1.9 mW [5], [8], [9] for exploratory research, due to the unavoidable employment of power-hungry PLL (commonly requiring >1 mW for sufficient phase noise performance) and the need for two identical baseband I/Q signal paths. Several sub-mW Cartesian receivers have been reported, yet featuring sensitivity worse than −90 dBm [10]- [12] or only reporting an RF front-end design without counting the power of PLL [10]- [14].…”

Section: Introductionmentioning

confidence: 99%

“…In[22], the square OTW shape [see subfigure (i) in Fig.3(b) above] does not make it sufficiently convincing to model the DCO output as a delayed version of input frequency, which is GFSK modulated 5. For sin(x), the Taylor series expansion is sin(x) ≈ x − x 3 3!…”

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confidence: 99%

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A 0.7-V Sub-mW Type-II Phase-Tracking Bluetooth Low Energy Receiver in 28-nm CMOS

Chen

Quinlan

et al. 2021

IEEE Trans. Circuits Syst. I

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We present an architecture of a Bluetooth low energy (BLE)-compliant receiver which, for the first time ever, breaks the 1 mW barrier of power consumption. It is based on a type-II phase-tracking loop and addresses the mutual magnetic coupling between on-chip inductors of a digitally controller oscillator (DCO) and low-noise transconductance amplifier (LNTA), which causes RX performance degradation in the priorart implementations. An inverter-based inductor-free LNTA is employed instead. The resulting adjacent channel rejection (ACR) improves by 1.5/2.5 dB at 2/3 MHz offset. By further leveraging current-reuse and switched-capacitor circuitry, this RX achieves the best-in-class FoM of 183.2 dB with sensitivity of −93.2 dBm. Thanks to the single-channel topology, the proposed RX occupies tiny area of 0.48 mm 2 in 28-nm CMOS. Index Terms-Bluetooth low energy (BLE) receivers (RXs), digitally controlled oscillator (DCO)-based receivers, discretetime (DT) receivers, Internet-of-Things (IoT), phase-tracking RXs (PT-RXs), inverter-based RXs, current-reuse, ultra-low power (ULP), ultra-low voltage (ULV).

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Section: Resultsmentioning

confidence: 99%

“…By substituting formula (11) into ( 9) and assuming Taylor series expansion, 5 the PD controller output is derived as follows,…”

Section: B Loop Delay Optimizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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A 0.7-V Sub-mW Type-II Phase-Tracking Bluetooth Low Energy Receiver in 28-nm CMOS

Chen

Quinlan

et al. 2021

IEEE Trans. Circuits Syst. I

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“…A good NF for state-of-the-art IoT receivers is 5-6dB [1][2][3][4][5][6]. In IoT receivers all blocks tend to contribute to the total power consumption [1][2][3][4][5][6][7][8][9][10]. Therefore, a fully optimized (system) design is required to obtain minimal power consumption.…”

Section: Introductionmentioning

confidence: 99%

2.4-GHz Highly Selective IoT Receiver Front End With Power Optimized LNTA, Frequency Divider, and Baseband Analog FIR Filter

Thijssen

Klumperink

Quinlan

et al. 2021

IEEE J. Solid-State Circuits

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High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4GHz ISM-band. In addition, low power consumption is very important for IoT receivers. We propose a 2.4GHz zero-IF receiver front-end architecture that reduces power consumption by 2× compared to state-of-the-art and improves selectivity by >20dB without compromising on other receiver metrics. To achieve this the entire receive chain is optimized. The LNTA is optimized to combine low noise with low power consumption. Stateof-the-art sub-30nm CMOS processes have almost equal strength complementary FETs, which result in altered design trade-offs. A Windmill 25%-duty cycle frequency divider architecture is proposed that uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog FIR filter is implemented to provide very high receiver selectivity with ultra low power consumption. The receiver front-end is fabricated in a 22nm FDSOI technology and has an active area of 0.5mm 2 . It consumes 370µW from a 700mV supply voltage. This low power consumption is combined with 5.5dB noise figure. The receiver front-end has -7.5dBm IIP3 and 1-dB gain compression for a -22dBm blocker; both at maximum gain of 61dB. From three channels offset onward the adjacent channel rejection is ≥63dB for BLE, BT5.0 and IEEE802.15.4.

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An N-Path Sub-GHz Ultra-Low Power Receiver Exploiting an N-Path Notch Filter Topology in 90 nm CMOS

Lei

et al. 2023

IEEE Access

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This paper describes an N-path sub-GHz ultra-low power receiver exploiting an N-path notch filter topology in 90nm CMOS process. The receiver achieves the flexibility in the operating frequency due to an adjustable internal impedance matching network with an N-path notch filter. The receiver consists of two current-reused topologies, which greatly simplifies the structure and achieves ultra-low power consumption. Specifically, the receiver incorporates: 1) an amplifier with an N-path notch filter, which acts as the first stage of the receiver to provide an input impedance of 50 Ω without an inductor. This input matching network is frequency flexible and adjustable to suit different frequencies of the input signal. Meanwhile, the N-path notch filter can suppress out-of-band interference to cope with limited frequency bands. 2) N-path passive mixers are reused for simultaneous filtering and down-conversion. 3) Amplifiers are frequency-division multiplexed to amplify both RF and baseband signals simultaneously. Finally, the receiver is fabricated in 90 nm CMOS and operates at 0.6 V supply voltage with a power consumption of 780 µW. The receiver achieves a conversion gain of 41.2 ± 3.2 dB, a noise figure of 5.7 ± 0.3 dB and an OB-IIP3 of 14.6 ± 0.5 dBm. The chip area of the implemented receiver is 0.08 µm 2 .INDEX TERMS CMOS, N-path notch filter, passive mixer, receiver, ultra-low power

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30.5 A 0.5V BLE Transceiver with a 1.9mW RX Achieving −96.4dBm Sensitivity and 4.1dB Adjacent Channel Rejection at 1MHz Offset in 22nm FDSOI

Cited by 26 publications

References 6 publications

A 0.7-V Sub-mW Type-II Phase-Tracking Bluetooth Low Energy Receiver in 28-nm CMOS

A 0.7-V Sub-mW Type-II Phase-Tracking Bluetooth Low Energy Receiver in 28-nm CMOS

2.4-GHz Highly Selective IoT Receiver Front End With Power Optimized LNTA, Frequency Divider, and Baseband Analog FIR Filter

An N-Path Sub-GHz Ultra-Low Power Receiver Exploiting an N-Path Notch Filter Topology in 90 nm CMOS

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