32nm high-density high-speed T-RAM embedded memory technology

Gupta, Rajesh; Nemati, F.; Robins, Scott; Yang, K.J.; Gopalakrishnan, V. K.; Sundarraj, Joseph John; Chopra, Rajesh; Roy, Rich; Cho, Hyun Jin; Maszara, W.; Mohapatra, Nihar R.; Wuu, John; Weiss, D.; Nakib, Sam

doi:10.1109/iedm.2010.5703345

Cited by 17 publications

(14 citation statements)

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“…Simulated I A versus V AH curve (t r = 50 ns) with and without a previous write-0 pulse. integration time of the anode current, which can be extremely short [5], [11] thanks to the orders-of-magnitude separation between the low and high current states of the memory cell. In addition to that, even the write-0 and write-1 operations can be very fast.…”

Section: Read and Write Operationsmentioning

confidence: 99%

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Modeling of Dynamic Operation of T-RAM Cells

Resnati

Compagnoni

Mulaosmanovic

et al. 2015

IEEE Trans. Electron Devices

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This paper presents a comprehensive simulation analysis of the dynamic operation of T-RAM cells. The analysis addresses the evolution of cell electrostatics and of carrier concentrations and flows in the device when the gate voltage undergoes a fast low-to-high switch, as required by both read and write operations. The results clarify, first of all, the basic physics making holes in the p-base the physical element allowing information storage in the device. From this starting point, the working principles exploited for DRAM operation of the memory cell are then explained. Index Terms-Forward breakover, gated thyristors, nanoscale semiconductor devices, semiconductor device modeling, thyristor RAM (T-RAM).

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Section: Read and Write Operationsmentioning

confidence: 99%

“…T HE T-RAM cell represents a promising memory solution for next generation DRAM devices [1]- [5]. The structure of this cell is that of a physical nanoscale thyristor with a gated p-base, whose bistability is exploited to reach, with the same voltage waveforms applied to its contacts, either of two stable states.…”

Section: Introductionmentioning

confidence: 99%

Modeling of Dynamic Operation of T-RAM Cells

Resnati

Compagnoni

Mulaosmanovic

et al. 2015

IEEE Trans. Electron Devices

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“…Despite clear benefits in terms of read/write times and process flow have been reported for this cell in comparison to state-of-the-art 1 Transistor -1 Capacitor devices [2], the reliability of T-RAM cells has never been comprehensively addressed up to now.…”

Section: Introductionmentioning

confidence: 99%

“…Nanoscale gated-thyristors have been recently proposed as promising memory elements for next-generation DRAM technologies [1]- [4], with the T-RAM cell representing the simplest and most advanced device structure [2]. Despite clear benefits in terms of read/write times and process flow have been reported for this cell in comparison to state-of-the-art 1 Transistor -1 Capacitor devices [2], the reliability of T-RAM cells has never been comprehensively addressed up to now.…”

Section: Introductionmentioning

confidence: 99%

Reliability investigation of T-RAM cells for DRAM applications

Mulaosmanovic

Paolucci

Compagnoni

et al. 2014

2014 IEEE International Reliability Physics Symposium

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In this work, we present a reliability investigation of T-RAM cells, considering their read failure, data retention and endurance. Experimental results on deca-nanometer devices reveal a successful cell operation solving the voltage trade-off for optimal performance on state-0 and state-1, whose origin is explained by clear pictures of the physical processes giving rise to read failure and limiting data retention. Moreover, endurance results appear very promising, with cell functionality preserved up to very high cycling doses.

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“…Fast operation is ensured by augmenting the thyristor with a MOS-like gate over the p-base. SRAM-like [3] and DRAM-like [4] TRAM cells and arrays were demonstrated in 130 nm and more recently in 32-nm Silicon on Insulator (SOI) CMOS technology [5], [6], and interest in TRAM has been growing [7], [8]. Another device suitable for TRAM-like applications is the so-called field-effect diode (FED) [9].…”

Section: Introductionmentioning

confidence: 99%

SOI FED-SRAM Cell: Structure and Operation

Badwan

Chbili

et al. 2015

IEEE Trans. Electron Devices

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A static memory cell (SRAM) based on the field-effect diode (FED) is presented, and its operation is explained with the help of numerical device simulations. Although this new cell resembles the thin-capacitively coupledthyristor (TCCT) SRAM cell in concept and operation, it is nevertheless characterized by significant advantages. These advantages derive from the fact that the thyristorlike mode of operation of the FED is gate induced, whereas the TCCT is an actual built-in thyristor. The operation of the cell is explained with the help of suitable timing diagrams, and the mechanisms of storing 1 and 0 are analyzed with detailed numerical simulations. In one operation scheme (where the cell could better be termed quasi-SRAM), a sequence of restore pulses is periodically applied after the cell is put on Hold, which ensures that the stored data remain valid for as long as the cell is powered ON. High read 0/1 current margin, fast write/read time, and densely packed cells are among the cell advantages obtained.Index Terms-SOI, Field-effect diode (FED), SRAM, thin-capacitively coupled thyristor (TCCT), thyristor.

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32nm high-density high-speed T-RAM embedded memory technology

Cited by 17 publications

References 0 publications

Modeling of Dynamic Operation of T-RAM Cells

Modeling of Dynamic Operation of T-RAM Cells

Reliability investigation of T-RAM cells for DRAM applications

SOI FED-SRAM Cell: Structure and Operation

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