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Major advancements in T-RAM cell manufacturability are reported. A fully planar implementation of a T-RAM cell is presented, which is easily integrated into a baseline 130nm SO1 CMOS logic technology by adding photo-mask and ionimplantation steps. The cell area of 0.562pm2 (33F2) is four times smaller than conventional 6T-SRAM. A new scheme, called Restore, significantly improves control of the cell standby current. Excellent T-RAM cell temperature stability is demonstrated between 0°C and 125°C. Measurement results from a 9Mb T-RAM test chip with full SRAM functionality show good bit yield, 2ns cell write speed, 1.711s cell read speed, and a cell standby current of -1 nA/Cell.

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