40-mm/sup 2/ 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory

Campardo, G.; Micheloni, Rino; Commodaro, S.; Yero, E.; Zammattio, M.; Mognoni, S.; Sacco, Andrew P.; Picca, M.; Manstretta, A.; Scotti, M.; Motta, I.; Golla, Carla; Pierin, A.; Bez, R.; Grossi, Alessandro; Modelli, Alberto; Visconti, A.; Khouri, O.; Torelli, G.

doi:10.1109/4.881212

Cited by 37 publications

(4 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Flash memory density is increased through a combination of multilevel-cell (MLC) approaches [5]- [9] and physical scaling [10]- [12]. MLC storage in flash memory using the well-established floating gate (FG) transistor was first reported in 1995 [5] to realize double density with the same process technology, and is acceptable for any given process technology generation [6]- [9]. A virtual-ground flash memory architecture [13] is proposed for significant scaling down of the cell size.…”

Section: Introductionmentioning

confidence: 99%

Scalable Virtual-Ground Multilevel-Cell Floating-Gate Flash Memory

Yamauchi

Kamakura

Matsuoka

2013

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

An adequate gate coupling ratio (GCR) and compensation for floating-gate to floating-gate (FG-to-FG) coupling interference must be maintained to enable further scaling of virtual-ground multilevel-cell (MLC) FG flash memory. A high GCR of 0.6 is obtained using a novel bowl-shaped FG structure cell technology without sacrificing cell size. Increasing the GCR is important for reducing FG-to-FG coupling interference and achieving low-voltage operation. A novel array segmented virtualground architecture with bit-line isolation between neighboring segments and two-step programming with the channel hot electron injection threshold voltage compensation technique are proposed to reduce the number of neighboring cells that are programmed after programming a given cell, as well as the amount of threshold voltage (V th ) shift of the neighboring cells. Adoption of this programming approach realizes a reduction in the V th shift caused by the FG-to-FG coupling interference < 25% in the bit-line direction, compared with conventional programming approaches, and the V th shift is almost completely eliminated in the word-line direction without sacrificing program throughput. The proposed virtual-ground MLC FG cell, which is as small as 3F 2 /bit (F is the minimum feature size) is successfully implemented into a test chip with good reliability.

show abstract

Section: Introductionmentioning

confidence: 99%

Scalable Virtual-Ground Multilevel-Cell Floating-Gate Flash Memory

Yamauchi

Kamakura

Matsuoka

2013

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

show abstract

“…Multilevel operation is a technique to increase the memory density by increasing the amount of information recorded in each memory cell from 1 bit to more than 2 bits [3,4]. As shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Analysis of the subthreshold characteristics for the FC‐SGT flash memory cell

Yamazaki

Nakamura

Sakuraba

et al. 2006

Electron Comm Jpn Pt II

View full text Add to dashboard Cite

SUMMARYIn this paper, an analytical model for finding the S-factor of the FC-SGT flash memory cell is derived. It is confirmed that the results of analysis agree well with the three-dimensional simulation results. In comparison with the conventional planar flash memory cell, the FC-SGT flash memory cell has a sufficiently smaller S-factor. As a result, it is easier to realize multilevel operation by the FC-SGT flash memory than by the conventional planar flash memory.

show abstract

“…Read access time and burst frequency have been improved and dual functionality has been obtained [2,3], in line with the requests of the most demanding wireless applications. The 2b/cell 256Mb memory in this paper features a 125MHz read burst speed and flexible read-whilewrite through the introduction of an voltage-ramp reading concept.…”

mentioning

confidence: 93%

A 125MHz burst-mode flexible readwhile-write 256Mbit 2b/c 1.8V NOR flash memory

Villa¹,

Vimercati²,

Schippers³

et al.

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.

View full text Add to dashboard Cite

Multilevel technology flash memory devices have been introduced [1] to obtain the low silicon cost and the high density required by a wide range of applications. Read access time and burst frequency have been improved and dual functionality has been obtained [2,3], in line with the requests of the most demanding wireless applications. The 2b/cell 256Mb memory in this paper features a 125MHz read burst speed and flexible read-whilewrite through the introduction of an voltage-ramp reading concept.The reading concept generally utilized in previously reported multilevel NOR products [4, 5] applies a fixed (5 to 6V) gate voltage to the matrix cell and to a set of reference cells whose threshold represents the boundary between the different levels. The sense amplifier(s) compare (in parallel or sequentially) the currents of the array cell with the reference and produces the two bits. The main challenge and drawback of this concept is tied to the wide current range in which the cell is required to operate (from few uA to several tens of uA). Large currents cause parasitic drops in the array and selector, cell gain variations have a major impact making difficult to narrow the levels to improve reliability and facilitate scaling. The proposed approach operates all cells in a low, fixed current range which minimizes the impact of parasitic resistances and of gain variations.A conventional NOR flash memory architecture is used. Reading and verify operations are performed applying a fast, linear voltage ramp to the reference and matrix cell's gate ( Fig. 2.5.1). The comparison of a local current reference against the cell's current produces a trigger. A time slot exists between two reference triggers. The matrix cell's level is determined by comparing the time difference between matrix and reference cells trigger points. The reference trigger information is driven to the matrix sense amplifiers as a digital bus. The trigger generated by the matrix sense amplifier latches the reference bus whose content digitally determines the cell level (11, 10, 01, 00).A double differential-stage sense amplifier (Fig. 2.5.2) is used. The first stage works as a pre-charger and current to voltage converter. The second stage is a differential comparator with a digital output. The sense amplifier pre-charges the bitline and as the pre-charging is completed, I ref will flow through the resistor R0. When the cell's V th is reached, the current through the bitline increases and when I bl is equal to I ref the sense amplifier produces the trigger; the cell is then cut off by lowering the drain voltage. Figure 2.5.3 further illustrates the operation: after bitline precharge, the voltage ramp turns on in sequence the three reference cells (R1,R2,R3) that cause the change of status of the digital bus. The digital bus is latched by the matrix sense amplifier trigger which is caused by I bl exceeding Iref ; the figure shows, as an example, the trigger point of few cells for each level. The dynamic nature of the voltage ramp (tunable in the range of 30n...

show abstract

40-mm/sup 2/ 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory

Cited by 37 publications

References 25 publications

Scalable Virtual-Ground Multilevel-Cell Floating-Gate Flash Memory

Scalable Virtual-Ground Multilevel-Cell Floating-Gate Flash Memory

Analysis of the subthreshold characteristics for the FC‐SGT flash memory cell

A 125MHz burst-mode flexible readwhile-write 256Mbit 2b/c 1.8V NOR flash memory

Contact Info

Product

Resources

About