512 Mb PROM with 8 layers of antifuse/diode cells

Crowley, Matthew; Al-Shamma, Ali; Bosch, D.; Farmwald, M.; Fasoli, L.; Ilkbahar, A.; Johnson, Mark; Kleveland, B.; Lee, T.; Liu, Tz-yi; Nguyen, Quang; Scheuerlein, R.E.; So, K.; Thorp, T.

doi:10.1109/isscc.2003.1234303

Cited by 24 publications

(6 citation statements)

References 1 publication

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“…It forms transistors inside on-chip interconnect layer [3], on poly-silicon films [18], or on single-crystal silicon films [32], [33]. Although a drastically high vertical interconnect density can be realized, it is not readily compatible to existing fabrication processes and is subject to severe process temperature constraints that tend to dramatically degrade the circuit electrical performance.…”

Section: Transistor Build-up 3d Technologymentioning

confidence: 99%

DSP Systems using Three-Dimensional (3D) Integration Technology

Zhang¹,

Pan²,

Li³

2010

Handbook of Signal Processing Systems

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As three-dimensional (3D) integration technology is quickly maturing and steadily entering mainstream markets, it has begun to attract exploding interest from integrated circuit and system designers. This chapter discusses and demonstrates the exciting opportunities and potentials for digital signal processing (DSP) circuit and system designers to exploit 3D integration technology. In particular, this chapter advocates a 3D logic-DRAM integration paradigm and addresses the use of 3D logic-memory integration in both programmable digital signal processors and application-specific digital signal processing circuits. To further demonstrate the potential, this chapter presents case studies on applying 3D logic-DRAM integration to clustered VLIW (very long instruction word) digital signal processors and application-specific video encoders. Since DSP systems using 3D integration technology is still in its research infancy, by presenting some first discussions and results, the aim of this chapter is to motivate greater future efforts from DSP system research community to explore this new and rewarding research area.

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Section: Transistor Build-up 3d Technologymentioning

confidence: 99%

DSP Systems using Three-Dimensional (3D) Integration Technology

Zhang¹,

Pan²,

Li³

2010

Handbook of Signal Processing Systems

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“…However, many RRAM studies conducted so far have been conducted in the high-current region (over 10 μA), making them unsuitable for future demanding electronic device applications [ 27 , 28 , 29 ]. The reason is that the reliability of the RRAM resistance state becomes difficult to achieve as the operating current decreases [ 30 , 31 , 32 , 33 ]. Approaches are being undertaken to overcome the reliability issue by adopting several types of electrodes or by changing the stacked structure [ 34 , 35 ], but there are still difficulties.…”

Section: Introductionmentioning

confidence: 99%

Quad-Level Cell Switching with Excellent Reliability in TiN/AlOx:Ti/TaOx/TiN Memory Device

et al. 2022

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TiN/AlOx:Ti/TaOx/TiN memory devices using bilayer resistive switching memory demonstrated excellent durability and capability of QLC (quad-level cell) memory devices. The best nonvolatile memory characteristics with the lowest operation current and optimized 4 bit/cell states were obtained using the Incremental Step Pulse Programming (ISPP) algorithm in array. As a result, a superior QLC reliability (cycle endurance > 1 k at each level of the QLC, data retention > 2 h at 125 °C) for all the 4 bits/cell operations was achieved in sub-μm scaled RRAM (resistive random access memory) devices.

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“…To enable readout of the state of the antifuse, the memory element must be insulating when deposited, but it should break down under electrical stress to a diode with high forward conductance. Cross-point memory arrays comprised of diode/antifuse elements can be addressed with diode logic schemes [2], [4] and could replace flash memory in a variety of applications.…”

Section: Introductionmentioning

confidence: 99%

Write-once diode/antifuse memory element with a sol-gel silica antifuse cured at low temperature

Branz²,

Stradins³

et al. 2005

IEEE Electron Device Lett.

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A write-once programmable memory element is based on a spin-coated sol-gel silica antifuse layer cured at 100 C. This antifuse is integrated with a thin-film silicon diode deposited at 160 C by hot-wire chemical vapor deposition. When a 3 to 5 V electrical pulse is applied across a diode/antifuse element, the silica breaks down suddenly and the current passing through the element increases irreversibly by more than about 10 4 . The on-state exhibits a diode-like current-voltage characteristic with a forward-reverse asymmetry of nearly 100 at 1 V and is stable if there was hexamethyldisilazane treatment of the wet-gel film before curing.Index Terms-Antifuse, electronic memory switching, sol-gel made silica, thin-film diode.

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512 Mb PROM with 8 layers of antifuse/diode cells

Cited by 24 publications

References 1 publication

DSP Systems using Three-Dimensional (3D) Integration Technology

DSP Systems using Three-Dimensional (3D) Integration Technology

Quad-Level Cell Switching with Excellent Reliability in TiN/AlOx:Ti/TaOx/TiN Memory Device

Write-once diode/antifuse memory element with a sol-gel silica antifuse cured at low temperature

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