2013
DOI: 10.1016/j.mee.2012.09.008
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56 nm pitch Cu dual-damascene interconnects with self-aligned via using negative-tone development Lithography-Etch-Lithography-Etch patterning scheme

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Cited by 13 publications
(5 citation statements)
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“…This integration solves viametal short yield and TDDB issues caused by LithoEtch-Litho-Etch (LELE) misalignment. [1]. However, Cu filling process is difficult because of patterned features' high aspect ratio.…”
Section: Introductionmentioning
confidence: 99%
“…This integration solves viametal short yield and TDDB issues caused by LithoEtch-Litho-Etch (LELE) misalignment. [1]. However, Cu filling process is difficult because of patterned features' high aspect ratio.…”
Section: Introductionmentioning
confidence: 99%
“…As the technology node advances, new integration schemes have to be used for the patterning of features below 80 nm pitch with 193 nm immersion lithography. In particular, thicker TiN-HM is necessary in order to ensure Self-Aligned-Via (SAV) integration which resolves via-metal short yield and TDDB issues caused by Litho-Etch-Litho-Etch (LELE) misalignment [2,3]. The Cu filling process is significantly more difficult if the thick TiN is not removed because of the high aspect ratio of the structures.…”
Section: Introductionmentioning
confidence: 99%
“…Thick-TiN-HM removal utilizing a SiCN retention scheme without Cu exposure was developed (Fig. 1(a)) and showed good electrical and reliability performance [3] but there still remains room for cost reduction for industrial challenges. In this paper, we demonstrated Thick-TiN-HM removal process by using all-in-one wet scheme (Fig.…”
Section: Introductionmentioning
confidence: 99%
“…This integration scheme was successfully used for a BEOL pitch down to 90 nm for the 28 nm node, however, for the 14 nm technology node, 64 nm BEOL minimum pitch is required for the first metal levels. Because it is unable to resolve features below 80 nm pitch in a single exposure, conventional 193 nm immersion lithography must be associated with dual patterning schemes, so called Lithography-Etch-Lithography-Etch (LELE) patterning [3] for line levels and self-aligned via (SAV) process [4] for via patterning. In both cases, 2 lithography/etch/clean sequences are necessary to obtain one desired pattern, and associated reworks also become more challenging since first pattern is exposed to resist removal processes (plasma + wet clean).…”
Section: Introductionmentioning
confidence: 99%