90nm SOI-CMOS of 150GHz f/sub max/ and 0.8dB NF/sub min/ @6GHz for SOC

Vanmackelberg,; Boret,; Glória,; Rozeau,; Gwoziecki,; Raynaud,; Lepilliet,; Dambrine,

doi:10.1109/soi.2002.1044456

Cited by 5 publications

(3 citation statements)

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“…Figure 6(a) compares the peak f T values predicted by our simulation with the ITRS targets and published experimental data for NMOS, SOI devices and FinFETs. Simulated f T values for planar SOI MOS devices reasonably fit the trend pattern of the experimental data [6][7][8][9][17][18][19][20][21][22][23][24][25][26][27][28][29][30] for planar MOSFETs published in the literature. New materials such as strained silicon could be used to achieve higher values of the drive current and cut-off frequency for nanoscale MOSFETs.…”

Section: Comparative Analysis Of Multi-gate Devicessupporting

confidence: 68%

Comparative analysis of nanoscale MOS device architectures for RF applications

Kranti¹,

Armstrong²

2007

Semicond. Sci. Technol.

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The suitability of nanoscale non-planar FinFETs and classical planar single and double gate SOI MOSFETs for rf applications is examined via extensive 3D device simulations and detailed interpretation. It is shown that although nanoscale FinFETs achieve higher values of intrinsic dc gain (nearly 20 dB higher than planar SG devices), they also present higher gate capacitance that severely undermines their rf performance. We also show that at large values of drain currents, well-designed conventional planar single and double gate SOI MOSFETs attain higher values of cut-off frequency compared to FinFETs, whereas at lower drain currents, a well-aligned planar double gate SOI MOSFET is the optimal structure. The reason for higher parasitic capacitance in FinFETs as compared to planar MOSFETs is examined in detail. An assessment of the impact of back gate misalignment on the rf performance of a 25 nm gate length planar double gate MOSFET indicates that a misalignment of 12 nm towards the source end is acceptable to give superior performance to a FinFET. The importance of source/drain extension region engineering in nanoscale FinFETs for ultra-low voltage analogue applications is also investigated. RF figures of merit for planar and vertical MOS devices are also compared based on layout-area calculations. The paper provides valuable design insights for optimizing device parameters for nanoscale planar and vertical MOSFETs.

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Section: Comparative Analysis Of Multi-gate Devicessupporting

confidence: 68%

Comparative analysis of nanoscale MOS device architectures for RF applications

Kranti¹,

Armstrong²

2007

Semicond. Sci. Technol.

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“…Portable devices find applications in almost all domains of life from household appliances to even controlling satellites. The efficient realization of a portable device demands that the entire system should be designed and fabricated on a 4 Author to whom any correspondence should be addressed. single substrate, called a system-on-chip (SoC).…”

Section: Introductionmentioning

confidence: 99%

“…The performance of an SoC can be further improved by using silicon-on-insulator (SOI) based BiCMOS technology. The advantages of SOI-BiCMOS technology include superior dc/ac isolation, reduced crosstalk and substrate noise and enhancement in the speed of operation of the device due to reduction in parasitic capacitances [4][5][6]. However, the use of high-performance vertical bipolar transistor in BiCMOS realization makes the technology more complex and costlier.…”

Section: Introductionmentioning

confidence: 99%

A high performance charge plasma based lateral bipolar transistor on selective buried oxide

Loan¹,

Bashir²,

Rafat³

et al. 2013

Semicond. Sci. Technol.

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In this paper, we present a new structure of lateral bipolar transistor on selective buried oxide. The device does not use highly doped regions; however, it employs the concept of creating n and p type charge plasma in undoped silicon by using metal electrodes of different work functions. The proposed device is named as the selective buried oxide based bipolar charge plasma transistor (SELBOX-BCPT). An extensive 2D simulation study has revealed that the proposed SELBOX-BCPT device not only possesses all the advantages of the conventional BCPT device, but it also addresses various severe problems of the BCPT device. A significant improvement in major issues of poor cutoff frequency ( f T ), low breakdown voltage and thermal efficiency has been achieved. It has been observed that the f T has increased by ∼94.6%, the breakdown voltage by 23.47% and the device is much cooler than the conventional BCPT device. A large current gain is obtained in the proposed device and is on a par with the conventional BCPT device. Further, by using mixed-mode simulation feature of the Atlas simulator, inverting amplifiers based on SELBOX-BCPT and the conventional BCPT have been realized. A significant improvement of 15% in switching-on transient time and 25.8% in switching-off transient time has been achieved in the proposed device in comparison to the conventional BCPT device.

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