RF and noise properties of SOI MOSFETs, including the influence of a direct tunneling gate current (invited)

Danneville, F.; Pailloncy, G.; Dambrine, G.; Iñíguez, B.

doi:10.1109/iccdcs.2004.1393363

Cited by 3 publications

(5 citation statements)

References 24 publications

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“…Furthermore, the flicker noise current power spectral density is also found to be increasing with increasing total width. In (20) or (21), it is clear that is inversely proportional to the total width of the transistor , while in (22), is directly dependent on the transistor's , which is also proportional to . Hence, the resultant geometry dependence of can be derived and shown to be only the transistor's total width , and this is clearly shown in the flicker noise measurement results.…”

Section: A Experimental Results and Discussionmentioning

confidence: 99%

“…In [22] and [23], the approximated expression for minimum noise factor is derived as shown in (10). In Section III-B, we will relate this expression to our measured .…”

Section: A Hf Noise Definition and Theorymentioning

confidence: 99%

“…Note that in ( 20) is bias independent, while in (21), is a bias-dependent parameter. Their corresponding noise current power spectral density can be found using (22) as follows:…”

Section: Unit Width Optimization On Flicker Noisementioning

confidence: 99%

See 2 more Smart Citations

RFCMOS Unit Width Optimization Technique

Tong¹,

Lim

Sia³

et al. 2007

IEEE Trans. Microwave Theory Techn.

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In this paper, we demonstrate a unit width ( ) optimization technique based on their unity short-circuit current gain frequency ( ), unilateral power gain frequency ( MAX ), and high-frequency (HF) noise for RFCMOS transistors. Our results show that the trend for the above figures-of-merit (FOMs) with respect to the change is different; hence, some tradeoff is required to obtain the optimum value. During the HF noise analysis, a new FOM is proposed to study the effect on the HF noise performance. In our experiment, the flicker noise of the transistor is also measured and the result shows that the change in does not affect the noise spectral density at the low-frequency range. This technique enables RF engineers to optimize the transistor's layout and helps to select the optimum for transistors used in specific circuit design such as the low-noise amplifier, voltage-controlled oscillator, and mixer. Furthermore, by using layout optimized transistors in the RF circuit, the optimal circuit's performance can be easily achieved and, thus, greatly reduced the circuit development time. In the aspect of RF device modeling, by knowing the optimum for a particular process or technology, the number of transistors to model is reduced and, hence, greatly shortens the RF modeling development time for existing and future technologies.

show abstract

Section: A Experimental Results and Discussionmentioning

confidence: 99%

“…In [22] and [23], the approximated expression for minimum noise factor is derived as shown in (10). In Section III-B, we will relate this expression to our measured .…”

Section: A Hf Noise Definition and Theorymentioning

confidence: 99%

See 1 more Smart Citation

RFCMOS Unit Width Optimization Technique

Tong¹,

Lim

Sia³

et al. 2007

IEEE Trans. Microwave Theory Techn.

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“…1) located across the gate conductance and its contribution to noise is modeled using two gate and drain shot noise sources [4,5]. These gate and drain shot noise sources can be expressed as:…”

Section: Gatementioning

confidence: 99%

Noise in SOI MOSFETs and Gate-All Around Transistors

Iñı́guez¹,

Lázaro²,

Hamid³

et al. 2005

AIP Conference Proceedings

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“…In [56], [57], the approximated expression for minimum noise factor (F min ) is derived as shown in (3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15). In the next section, we will relate this expression to our measured NF min parameter.…”

Section: Structurementioning

confidence: 99%

Design of a scalable RF model for deep sub-micron mosfets

Tong¹

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In order to achieve first pass design success and optimized RF circuit design, the process design kit (PDK) provided by the foundry must be equipped with accurate and scalable RF models for circuit simulation and optimization process. However, existing RF MOSFET models provided by most foundries are usually in discrete sizes. This poses many design problems for the integrated circuit (IC) designers because certain transistors' geometry sizes are not available in the PDK. Design optimization is not possible without scalable RFCMOS models and the circuit performance cannot be optimized for a particular technology node used for circuit fabrication. Furthermore, discrete RFCMOS models will limit the design flexibility and increase the difficulty in designing RF circuit blocks to meet more stringent design specifications as the operating frequency increases. Currently in the industry, the RF MOSFET model that was developed is mainly in BSIM3v3 and BSIM4 models. In BSIM3v3, the RF model is developed by macro modeling approach whereby sub-circuit components are added to the core transistor model. In BSIM4, the RF model for the parasitic components were developed and included into the source code of the core model. Therefore, theoretically, there is no need for the addition of the sub-circuit components as in BSIM3v3 RF model. Although these two RF models are able to simulate the transistor's S-parameters, the sub-circuit components used are of discrete values. Thus, scalable RF modeling is still not achieved. Therefore, there is a need to study how to develop a scalable and physical RF MOSFET model. Most of the RF models are developed based on the macro modeling approach. Using this approach, sub-circuit components are added to the transistor's

show abstract

RF and noise properties of SOI MOSFETs, including the influence of a direct tunneling gate current (invited)

Cited by 3 publications

References 24 publications

RFCMOS Unit Width Optimization Technique

RFCMOS Unit Width Optimization Technique

Noise in SOI MOSFETs and Gate-All Around Transistors

Design of a scalable RF model for deep sub-micron mosfets

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