A 0.05 μm-CMOS with ultra shallow source/drain junctions fabricated by 5 keV ion implantation and rapid thermal annealing

Hori, Atsushi; Nakaoka, H.; Umimoto, H.; Yamashita, K.; Takase, Masami; Shimizu, Naoji; Mizuno, B.; Odanaka, S.

doi:10.1109/iedm.1994.383363

Cited by 28 publications

(9 citation statements)

References 6 publications

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“…In 1994, a standard production implanter was used to fabricate fully functional CMOS transistors with 50 nm gate dimensions ͑and 3.1 nm gate oxide͒ using scaled spacer lightly doped drain ͑LDD͒ and channel-pocket implants along with heavily doped, Ti salicide-capped source/drains. 162 Although many other techniques are under active investigation ͓plasma immersion implantation, vapor or solid-source diffusion with rapid thermal annealing ͑RTA͒, gas-immersion laser doping͔, the dominant method of doping remains the direct ion implantation of dopants into Si with a beamline technology. In the following, we break up the challenges for scaling of shallow junctions into ͑1͒ development of technology for production-worthy, low-energy ion beam tools and ͑2͒ control of materials issues such as dopant diffusion and activation and defect annealing with low thermal budgets.…”

Section: Shallow Junctions: Machine and Processing Constraintsmentioning

confidence: 99%

Ion beams in silicon processing and characterization

Chason

Picraux

Poate

et al. 1997

Journal of Applied Physics

262

106

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General trends in integrated circuit technology toward smaller device dimensions, lower thermal budgets, and simplified processing steps present severe physical and engineering challenges to ion implantation. These challenges, together with the need for physically based models at exceedingly small dimensions, are leading to a new level of understanding of fundamental defect science in Si. In this article, we review the current status and future trends in ion implantation of Si at low and high energies with particular emphasis on areas where recent advances have been made and where further understanding is needed. Particularly interesting are the emerging approaches to defect and dopant distribution modeling, transient enhanced diffusion, high energy implantation and defect accumulation, and metal impurity gettering. Developments in the use of ion beams for analysis indicate much progress has been made in one-dimensional analysis, but that severe challenges for two-dimensional characterization remain. The breadth of ion beams in the semiconductor industry is illustrated by the successful use of focused beams for machining and repair, and the development of ion-based lithographic systems. This suite of ion beam processing, modeling, and analysis techniques will be explored both from the perspective of the emerging science issues and from the technological challenges.

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Section: Shallow Junctions: Machine and Processing Constraintsmentioning

confidence: 99%

Ion beams in silicon processing and characterization

Chason

Picraux

Poate

et al. 1997

Journal of Applied Physics

262

106

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“…However, individual devices with channel length below 50 nm have already been fabricated and characterized by several research groups [2], [3]. Full scale complementary metal-oxide-semiconductor (CMOS) technology based on 50 nm transistors has also been reported [4]. The steady lowering of the supply voltages, to reduce the power consumption and to hold the reliability, will make the systems based on such devices more sensitive to fluctuations in the device characteristics.…”

Section: Introductionmentioning

confidence: 99%

Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFET's: A 3-D "atomistic" simulation study

Asenov

1998

IEEE Trans. Electron Devices

595

315

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“…Therefore, n-adder gate delay time is [9] : 1 + 2 + 4 (k-1) + 2=4k+1, which is greatly reduced compared to the 2n gates levels delay time that serial adder produced. Under the room temperature 2.5V, 100nm and 1.5V, the delay time of 50nm the CMOS gate has respectively achieved 11.8ps [10] and 13.1ps [11] , therefore the time which accomplishing big number addition operation is only several nanoseconds, this is quite to the time of circulation shift.…”

Section: The Design Of Fast Addermentioning

confidence: 97%

Improvement of modular multiplication algorithm based on sliding window

Chen

Fang

2007

SPIE Proceedings

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The paper makes a conclusion that the key to increase the speed of large number modular multiplication is not only to decrease the time of addition, but also to decrease the time of circulation shift. According to the analysis of the principle implement and time complexity of sliding window algorithm which is more speed, it presents a improving method about sliding window algorithm to decrease the time of addition and circulation shift by decreasing the judgment on carry sign and increasing the width of one circulation shift and implements the high speed calculation of modular multiplication algorithm.

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A 0.05 μm-CMOS with ultra shallow source/drain junctions fabricated by 5 keV ion implantation and rapid thermal annealing

Cited by 28 publications

References 6 publications

Ion beams in silicon processing and characterization

Ion beams in silicon processing and characterization

Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFET's: A 3-D "atomistic" simulation study

Improvement of modular multiplication algorithm based on sliding window

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