A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO

Minami, K.; Fukaishi, M.; Mizuno, Masayuki; Onishi, H.; Noda, K.; Imai, K.; Horiuchi, Takeshi; Yamaguchi, Haruhisa; Sato, Takahiro; Nakamura, K.; Yamashina, M.

doi:10.1109/cicc.2001.929758

Cited by 9 publications

(9 citation statements)

References 5 publications

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“…If low-devices were available in the process technology, using one for the follower would further improve the gain linearity at high VCO frequencies. The -converter in [9] achieves a linear gain for the entire range of , slightly larger than the range of this proposed -converter. However, the -converter in [9] suffers from high power-supply noise sensitivity due to the coupling of to both ground and .…”

Section: A Vco Designmentioning

confidence: 94%

“…The -converter in [9] achieves a linear gain for the entire range of , slightly larger than the range of this proposed -converter. However, the -converter in [9] suffers from high power-supply noise sensitivity due to the coupling of to both ground and . The gain linearity improvement technique proposed in this paper resolves the problem by coupling only to the ground reference.…”

Section: A Vco Designmentioning

confidence: 94%

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A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation

Mansuri

Yang

2003

IEEE J. Solid-State Circuits

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This paper describes a fully integrated low-jitter CMOS phase-locked loop and clock buffer for low-power digital systems with a wide range of operating frequencies. The design uses static CMOS inverters as a building block of the voltage-controlled oscillator and clock buffering. To reduce supply-induced jitter, programmable circuits with opposite sensitivity compensate for the delay variations. Both elements have supply-induced delay sensitivity of 0 1% delay 1% DD. The design is fabricated in 0.25m CMOS technology and consumes 10 mW from a 2.5-V supply. The experimental results verify that the proposed methods significantly improve the jitter.

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Section: A Vco Designmentioning

confidence: 94%

Section: A Vco Designmentioning

confidence: 94%

A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation

Mansuri

Yang

2003

IEEE J. Solid-State Circuits

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“…Recently, circuit design techniques to compensate the gate tunneling leakage of MOS capacitor in PLL have been reported in nanoscale CMOS processes [3]- [7]. The MOS capacitor realized with thick oxide has a less gate tunneling leakage [3]. The capacitor with multimetal structure was used to avoid the gate tunneling leakage [4].…”

Section: Introductionmentioning

confidence: 99%

“…The MOS capacitor with a larger capacitance per area was often used in PLL to reduce the silicon cost, but the PLL performance is degraded due to the large gate tunneling leakage. Recently, circuit design techniques to compensate the gate tunneling leakage of MOS capacitor in PLL have been reported in nanoscale CMOS processes [3]- [7]. The MOS capacitor realized with thick oxide has a less gate tunneling leakage [3].…”

Section: Introductionmentioning

confidence: 99%

Impact of Gate Tunneling Leakage on Performances of Phase Locked Loop Circuit in Nanoscale CMOS Technology

Chen

Ker

2007

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual

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The influence of gate tunneling leakage on the circuit performances of phase locked loop (PLL) in nanoscale CMOS technology has been investigated by simulation. The basic PLL with second-order loop filter is used to simulate the impact of gate tunneling leakage on performance degradation of PLL in a standard 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate this impact to PLL. The locked time, static phase error, and jitter of second-order PLL are degraded by the gate tunneling leakage of MOS capacitor in loop filter.

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“…The digital switching noise coupled through power supply and substrate induces considerable noise into noise-sensitive analog circuits [1], [3]- [7]. Many analog approaches are proposed to improve the jitter performance of PLLs, such as choosing a narrow bandwidth or using a low-gain voltage-controlled oscillator (VCO) [5].…”

Section: Introductionmentioning

confidence: 99%

An all-digital phase-locked loop for high-speed clock generation

Chung

Lee

2003

IEEE J. Solid-State Circuits

182

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Abstract-An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented in this brief. The proposed ADPLL architecture uses both a digital control mechanism and a ring oscillator and, hence, can be implemented with standard cells. The ADPLL implemented in a 0.3-m one-poly-four-metal CMOS process can operate from 45 to 510 MHz and achieve worst case frequency acquisition in 46 reference clock cycles. The power dissipation of the ADPLL is 100 mW (at 500 MHz) with a 3.3-V power supply. From chip measurement results, the -jitter of the output clock is 70 ps, and the root-mean-square jitter of the output clock is 22 ps. A systematic way to design the ADPLL with the specified standard cell library is also presented in this brief. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for system-on-chip applications.Index Terms-All-digital phase-locked loop (ADPLL), clock generator, frequency synthesizer, HDL, low jitter.

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A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO

Cited by 9 publications

References 5 publications

A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation

A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation

Impact of Gate Tunneling Leakage on Performances of Phase Locked Loop Circuit in Nanoscale CMOS Technology

An all-digital phase-locked loop for high-speed clock generation

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