A 0.168μm/sup 2/0.11μm/sup 2/ highly scalable high performance embedded DRAM cell for 90/65-nm logic applications

Wang, G.; Parries, P.; Khan, Babar A.; Liu, J.; Otani, Yohei; Norum, J.; Robson, N.; Kirihata, T.; Iyer, Subramanian S.

doi:10.1109/vtsa.2005.1497070

Cited by 4 publications

(6 citation statements)

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“…This instance of the defect is water soluble and is easily removed by a water rinse, which can be added as a process step post RIE. A similar case of bromine contamination was found after etching deep trenches such as used for embedded dynamic random access memory (eDRAM) [4]. For the eDRAM structures it was found that the remaining bromine caused etching of the oxide or blocking of deposition of the material to contact the deep trench capacitor.…”

Section: Condensation Defectsmentioning

confidence: 71%

Reducing Environmentally Induced Defects While Maintaining Productivity

Roijen

Conti

Keyser

et al. 2013

IEEE Trans. Semicond. Manufact.

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In semiconductor manufacturing, we expect the cause of defects to be process or tool related. However, at the 90 nm technology node and beyond we find that defects can be caused by issues related to the wafers' environment, such as processing of other wafers in the same tool or in the same carrier, or by seemingly innocuous actions. We pay special attention to the role of the mini-environment, which is deemed essential to achieving low particle counts for advanced technology nodes. We show defects that are caused by the environment, and some which are specifically related to the use of the mini-environment. We discuss several ways to reduce the sensitivity to environmental factors. Process and tool changes are found that eliminate yield detractors. We also present a workaround that has helped reduce the impact of queue time restrictions on cycle time.

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Section: Condensation Defectsmentioning

confidence: 71%

Reducing Environmentally Induced Defects While Maintaining Productivity

Roijen

Conti

Keyser

et al. 2013

IEEE Trans. Semicond. Manufact.

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“…For LP-DRAM, we obtain technology data by extrapolating published data of 180/130/90/65nm LP-DRAM processes [12,38]. For COMM-DRAM, we obtain technology data by using projections from the ITRS and other sources [3,23,24].…”

Section: Dram Modelingmentioning

confidence: 99%

“…We assume that SRAM cells use long-channel ITRS HP transistors, similar to that employed in the 65nm Intel Xeon L3 cache [8]. We assume that COMM-DRAM cells employ conventional thick oxide based transistors, and LP-DRAM cells employ intermediate oxide based transistors similar to that described in [38]. For the peripheral and global support circuitry of the RAMs, we assume that SRAMs and LP-DRAMs use ITRS long-channel HP transistors while COMM-DRAMs use LSTP transistors [23].…”

Section: Dram Modelingmentioning

confidence: 99%

“…Table 1 shows the areas we have assumed for SRAM, LP-DRAM, and COMM-DRAM cells. The LP-DRAM cells presented in [38] for four different technology nodes -180/130/90/65nm -have areas in the range of 19-26F 2 . In contrast, a typical SRAM cell would have an area of about 120-150F 2 .…”

Section: Cellmentioning

confidence: 99%

“…In contrast, commodity DRAM (COMM-DRAM) used in main memory chips is fabricated in its own commodity DRAM fabrication process. Compared to COMM-DRAM technology, LP-DRAM technology typically has faster transistors and circuitry but worse cell density and retention time [38]. These different technology characteristics translate into different area, delay, and energy properties for LP-DRAM and COMM-DRAM memories with identical functional specifications.…”

Section: Introductionmentioning

confidence: 99%

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A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

Thoziyoor

Ahn

Monchiero

et al. 2008

2008 International Symposium on Computer Architecture

173

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In this paper we introduce CACTI-D, a significant enhancement of CACTI 5.0. CACTI-D adds support for modeling of commodity DRAM technology and support for main memory DRAM chip organization. CACTI-D enables modeling of the complete memory hierarchy with consistent models all the way from SRAM based L1 caches through main memory DRAMs on DIMMs.We illustrate the potential applicability of CACTI-D in the design and analysis of future memory hierarchies by carrying out a last level cache study for a multicore multithreaded architecture at the 32nm technology node. In this study we use CACTI-D to model all components of the memory hierarchy including L1, L2, last level SRAM, logicprocess based DRAM or commodity DRAM L3 caches, and main memory DRAM chips. We carry out architectural simulation using benchmarks with large data sets and present results of their execution time, breakdown of power in the memory hierarchy, and system energy-delay product for the different system configurations. We find that commodity DRAM technology is most attractive for stacked last level caches, with significantly lower energy-delay products.

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Voltage-controlled magnetic tunnel junctions with synthetic ferromagnet free layer sandwiched by asymmetric double MgO barriers

Grèzes

Wong

et al. 2019

J. Phys. D: Appl. Phys.

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Memory and computing applications utilizing voltage-controlled magnetic random-access memory (MRAM) require perpendicular magnetic tunnel junctions (pMTJs) capable of high thermal stability and large write efficiency at advanced technology nodes. We first discuss the scaling requirements for voltage-controlled MRAM to replace various existing memory applications at an advanced CMOS technology node, including cell size, thermal stability, interfacial perpendicular magnetic anisotropy (PMA), and voltage-controlled magnetic anisotropy (VCMA). For replacing volatile memories including SRAM, eDRAM, and DRAM, we employ the retention relaxation technique along with a DRAM-style refresh scheme in the analysis. To enhance both PMA and VCMA at scaled nodes, we explore pMTJs with asymmetric double MgO barriers sandwiching a synthetic ferromagnet (SyF) free layer. In a thin MgO/SyF free layer/thick MgO/fixed layer MTJ stack, the SyF free layer is realized in various ways: single layer (X = Ta, W, Mo, Ir) and bilayers (X = Ta/W, Mo/Ir) of heavy metals insertions in CoFeB/X/CoFeB and Co2FeAl/X/Co2FeAl structures, and multiple insertions in [CoFeB/X]n/CoFeB structures for n = 1–4. A VCMA coefficient of 36 fJ (V m)−1 is achieved in a MgO/CoFeB/Ta/CoFeB/MgO-based MTJ which is comparable to that of the single MgO barrier MTJ. We find PMA enhancement, although with VCMA reduction for an increasing number n of [CoFeB/X]n repetitions. In addition, we demonstrate large TMR of 78%, large interfacial PMA of 1.45 mJ m−2, and VCMA of 65 fJ (V m)−1 in a MgO/Co2FeAl/W/Co2FeAl/MgO-based MTJ annealed above 400 °C.

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A 0.168μm/sup 2/0.11μm/sup 2/ highly scalable high performance embedded DRAM cell for 90/65-nm logic applications

Cited by 4 publications

References 1 publication

Reducing Environmentally Induced Defects While Maintaining Productivity

Reducing Environmentally Induced Defects While Maintaining Productivity

A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

Voltage-controlled magnetic tunnel junctions with synthetic ferromagnet free layer sandwiched by asymmetric double MgO barriers

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