A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist

Lu, Chien-Yu; Chuang, Ching-Te; Jou, Shyh-Jye; Tu, Ming-Hsien; Wu, Yaping; Huang, Chung-Ping; Kan, Paul-Sen; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin

doi:10.1109/tvlsi.2014.2318518

Cited by 34 publications

(19 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To show the effectiveness of the SEDF10T SRAM cell, important design metrics are extracted using 65-nm CMOS technology on Cadence. For comparison of the design metrics, the authors also designed and simulated the conv 6T (Figure 1a), ST-2 cell (Figure 1c) [6], TPDF9T cell ( Figure 1d) [7], and power-gated 9T cell (hereafter referred to as the PG9T cell) ( Figure 1e) [8] with 65 -nm CMOS technology. For the conv 6T cell, width of pull-down, access, and pull-up transistors is equal to 300 nm, 200 nm, and 150 nm, respectively.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

See 1 more Smart Citation

A data-aware write-assist 10T SRAM cell with bit-interleaving capability

Mansore¹,

Gamad²

2018

Turk J Elec Eng & Comp Sci

View full text Add to dashboard Cite

Cell stability is becoming an important design concern as process technology continues to scale down. In this paper, we present a single-ended 10T SRAM cell that improves simultaneously both read static noise margin (RSNM) and write static noise margin (WSNM) by employing separate read buffer and power gating transistors, respectively. The cross-point write structure of the proposed cell facilitates bit-interleaved architecture to enhance soft-error immunity. Simulation is done on 65-nm CMOS technology on Cadence. Simulation results show that the RSNM of the proposed SRAM cell is 2.78 times and 1.47 times higher than those of the conventional 6T and Schmitt trigger-based 10T (ST-2) cells, respectively, at 0.4 V. The WSNM of the proposed design is 5.14 times larger than that of the two-port disturbfree 9T (TPDF9T) cell (without write assist) at 0.4 V. Write delay of the proposed cell is 77.56% less than that of the TPDF9T cell at 0.4 V. Leakage power dissipation of the proposed SRAM cell is 0.89 times that of the ST-2 cell at 0.4 V. The proposed cell occupies 1.34 times more area than the conventional 6T cell.

show abstract

Section: Simulation Results and Discussionmentioning

confidence: 99%

“…Section 4 provides a conclusion. (a) Conventional 6T cell, (b) read-decoupled 8T cell [5], (c) ST-2 cell [6], (d) TPDF9T cell[7], and (e) power-gated 9T cell[8].…”

mentioning

confidence: 99%

A data-aware write-assist 10T SRAM cell with bit-interleaving capability

Mansore¹,

Gamad²

2018

Turk J Elec Eng & Comp Sci

View full text Add to dashboard Cite

show abstract

“…It is particularly eligible for power-efficient applications where the power consumption is highly constrained while the performance requirement is secondary. Accordingly, many power-hungry digital systems [5][6][7][8][9] and low-power memories [10][11][12][13][14] benefit tremendously from sub-threshold circuits.…”

Section: Introductionmentioning

confidence: 99%

65 nm sub‐threshold logic standard cell library using quasi‐Schmitt‐trigger design scheme and inverse narrow width effect aware sizing

Wen¹,

Liu²,

Zhang³

et al. 2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

In this study, the authors propose a sub-threshold standard cell library in which the quintessence is a quasi-Schmitttrigger logic design scheme and the inverse narrow width effect aware sizing method. The techniques can improve the I onto -I off ratio of the logic cells effectively and provide a significant suppression in leakage current, enhancing the robustness of the circuits. Simulation results show that the NAND3 and NOR3 logics with the new techniques achieve 40-60% and 30-50% reductions in leakage power compared with conventional logic circuits, respectively, when the voltage is scaled down to subthreshold region. Again, they also exhibit considerable improvements in process variation immunity and power-delay product.

show abstract

“…However, the writeability and write time are degraded owing to their stacked access transistors. Therefore, write assist techniques are required for CP cells to improve the write-ability in low voltage regions [10,11].…”

Section: Introductionmentioning

confidence: 99%

“…However, the write‐ability and write time are degraded owing to their stacked access transistors. Therefore, write assist techniques are required for CP cells to improve the write‐ability in low voltage regions [10, 11]. Nevertheless, the effectiveness of the additional assist circuits is influenced by the process voltage and temperature (PVT) variations as well.…”

Section: Introductionmentioning

confidence: 99%

Single bit‐line 8T SRAM cell with asynchronous dual word‐line control for bit‐interleaved ultra‐low voltage operation

Huang

Chiou

2018

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

This study proposes a single bit-line and disturbance-free static random-access memory (SRAM) cell for ultra-low voltage applications. SRAM cell with read-decoupled and cross-point structure addresses both the read-disturb and half-select stability issues; nevertheless, the write-ability is degraded due to the stacked pass transistors. In this study, the authors propose a single-ended 8T bit-cell and dual word-line control technique that can simultaneously improve the read stability, half-select stability, and write-ability without additional peripheral circuits, which is advantageous for bit-interleaved ultra-low voltage operations. A 4 kb test chip was implemented in a 90 nm complementary metal-oxide-semiconductor process to verify the proposed design. Silicon measurements indicate that the proposed design can operate at a voltage as low as 360 mV with 2.68 μW power consumption.

show abstract

A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist

Cited by 34 publications

References 23 publications

A data-aware write-assist 10T SRAM cell with bit-interleaving capability

A data-aware write-assist 10T SRAM cell with bit-interleaving capability

65 nm sub‐threshold logic standard cell library using quasi‐Schmitt‐trigger design scheme and inverse narrow width effect aware sizing

Single bit‐line 8T SRAM cell with asynchronous dual word‐line control for bit‐interleaved ultra‐low voltage operation

Contact Info

Product

Resources

About