A 0.4 V 63 &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\mu$&lt;/tex&gt;&lt;/formula&gt;W 76.1 dB SNDR 20 kHz Bandwidth Delta-Sigma Modulator Using a Hybrid Switching Integrator

Yoon, Younghyun; Choi, Danbi; Roh, Jeongjin

doi:10.1109/jssc.2015.2468857

Cited by 24 publications

(16 citation statements)

References 33 publications

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“…The capacitor values used in the DSM are summarized in Table 2. The first integrator is the most important block in a DSM-it also has the largest power dissipation [10,11]. Because the noise-shaping characteristics of the first integrator are not as good as those of other integrators [10], it is very important to improve the performance of the first integrator to achieve high performance.…”

Section: Feedforward Coefficientsmentioning

confidence: 99%

A 103 dB DR Fourth-Order Delta-Sigma Modulator for Sensor Applications

2019

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This paper describes a fourth-order cascade-of-integrators with feedforward (CIFF) single-bit discrete-time (DT) switched-capacitor (SC) delta-sigma modulator (DSM) for high-resolution applications. This DSM is suitable for high-resolution applications at low frequency using a high-order modulator structure. The proposed operational transconductance amplifier (OTA), used a feedforward amplifier scheme that provided a high-power efficiency, a wider bandwidth, and a higher DC gain compared to recent designs. A chopper-stabilization technique was applied to the first integrator to remove the 1/f noise from the transistor, which is inversely proportional to the frequency. The designed DSM was implemented using 0.35 µm complementary metal oxide semiconductor (CMOS) technology. The oversampling ratio (OSR) was 128, and the sampling frequency was 128 kHz. At a 500 Hz bandwidth, the signal-to-noise ratio (SNR) was 100.3 dB, the signal-to-noise distortion ratio (SNDR) was 98.5 dB, and the dynamic range (DR) was 103 dB. The measured total power dissipation was 99 µW from a 3.3 V supply voltage.

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Section: Feedforward Coefficientsmentioning

confidence: 99%

A 103 dB DR Fourth-Order Delta-Sigma Modulator for Sensor Applications

2019

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“…Delta-sigma modulators (DSMs) are widely used in audio applications for high-resolution analog-to-digital conversion [9,10,11]. ULV DSMs operating at a supply voltage of around 0.5 V or below have been reported in [12,13,14,15,16,17,18,19,20,21,22,23,24]. Most of the ULV DSMs are realized by switched-capacitor (SC) circuits.…”

Section: Introductionmentioning

confidence: 99%

“…The discrete-time (DT) DSMs in [14,15] employ clock boosting technique to reduce the distortion, but it can cause long-term reliability issues in the advanced process. The 0.4-V DT DSMs in [16,17] employ a mixed differential difference amplifier integrator and a hybrid switching integrator respectively to operate at ULV without a clock boosting circuit. However, the achieved SNDR in [16] is degraded by its complicated switching and noise, and the switch placed in signal input path in [17] can cause distortion during input signal integration phase as its on-resistance still varies with the input signal and the process corner.…”

Section: Introductionmentioning

confidence: 99%

A 0.4-V 0.2 pJ/step 90-dB SNDR 20-kHz CT delta-sigma modulator using class-AB amplifier with a novel local common-mode feedback

Chen

Wang

Zhang

et al. 2019

IEICE Electron. Express

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This paper presents a 0.4-V continuous-time delta-sigma modulator for high-quality power-efficient audio applications. A new ultra-low voltage amplifier for high linearity and low power consumption is proposed by exploring class-AB topology with a novel local common-mode-feedback loop. A low V T self-body-biased PMOS switch is employed in feedback digital-to-analog converter to improve the linearity performance against PVT-induced on resistance variation, which avoids clock boosting that may harm long-term reliability. A simple and robust non-overlapping clock generation circuit is proposed for high SNDR performance of modulator at 0.4-V or below. Fabricated in a 130-nm CMOS process, the modulator achieves 90.2 dB signal-to-noise-plus-distortion ratio (SNDR) with 0.2 pJ/step Figure-of-Merit (FoM) over a 20-kHz signal bandwidth, outperforming the reported audio delta-sigma modulators operating at 0.5-V or below. Furthermore, the modulator can operate with a supply down to 0.34-V while achieving an 86.1 dB SNDR at 0.17 pJ/step.

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“…The sigma‐delta analog‐to‐digital converter (SD‐ADC) is the main candidate for high‐resolution applications due to their noise shaping mechanism and inherent immunity to the circuit nonidealities and has been widely used in many applications, such as communication systems, audio signal processing, and biomedical imaging systems . For the wideband applications, such as the popular medical ultrasound imaging (1‐15 MHz), the multistage noise shaping (MASH) structure is ideally suitable due to its potential for achieving higher resolution performance, wideband operation, and system stability .…”

Section: Introductionmentioning

confidence: 99%

“…The sigma-delta analog-to-digital converter (SD-ADC) is the main candidate for high-resolution applications due to their noise shaping mechanism and inherent immunity to the circuit nonidealities [1][2][3] and has been widely used in many applications, such as communication systems, [4][5][6] audio signal processing, [7][8][9] and biomedical imaging systems. [10][11][12] For the wideband applications, such as the popular medical ultrasound imaging (1)(2)(3)(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)(14)(15), the multistage noise shaping (MASH) structure is ideally suitable due to its potential for achieving higher resolution performance, wideband operation, and system stability. 13 The linearity and SNDR of the modulator are expected to be as high as possible so that the imaging system could capture the analog biomedical input signal in its most original form and enhance the performance of imaging.…”

Section: Introductionmentioning

confidence: 99%

A 15‐MHz bandwidth double sampling MASH2_5b‐1_5b sigma‐delta modulator with DEM for multibit DACs

Fei

Zhang

et al. 2019

Circuit Theory & Apps

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Summary A high SNDR discrete‐time (DT) 2‐1 MASH sigma‐delta modulator (SDM) for 15‐MHz bandwidth was presented. Cascade of integrators with feedforward (CIFF) scheme, combined with the optimized gain coefficients, was adopted to avoid of the integrators. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. Five‐bit flash quantizer was adopted in both stages to improve the overall signal‐to‐noise and distortion ratio (SNDR) performance, and third‐order dynamic element matching (DEM) was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated in a mature 0.18‐μm CMOS technology, the occupied area of the modulator was 0.24 mm2 and dissipation power 25.4 mW from a 1.8‐V voltage supply. As a sampling rate of 240 MHz for the input sampling and DAC and 480 MHz for the flash ADC, a SNDR of 90.2 dB over 15‐MHz signal bandwidth and the corresponding effective number of bits (ENOB) of 14.69 bit were achieved. The spurious‐free dynamic range (SFDR) was 98 dB with DEM turned on for a 3.75 MHz at −2.5‐dBFS input signal, and the figure of merit (FOM) was 30.7 fJ/conv. for 15‐MHz bandwidth. A 15‐MHz bandwidth multibit MASH2‐1 discrete‐time sigma‐delta modulator was proposed. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. High‐order DEM was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated by a 0.18‐μm CMOS process, the modulator achieved a SNDR of 90.2 dB and the corresponding ENOB 14.69 bit over 15‐MHz signal bandwidth. The proposed modulator was very suitable for wideband applications including wireless communication systems, high‐frequency biomedical imaging or sensing systems, and so on.

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A 0.4 V 63 <formula formulatype="inline"><tex Notation="TeX">$\mu$</tex></formula>W 76.1 dB SNDR 20 kHz Bandwidth Delta-Sigma Modulator Using a Hybrid Switching Integrator

Cited by 24 publications

References 33 publications

A 103 dB DR Fourth-Order Delta-Sigma Modulator for Sensor Applications

A 103 dB DR Fourth-Order Delta-Sigma Modulator for Sensor Applications

A 0.4-V 0.2 pJ/step 90-dB SNDR 20-kHz CT delta-sigma modulator using class-AB amplifier with a novel local common-mode feedback

A 15‐MHz bandwidth double sampling MASH2_5b‐1_5b sigma‐delta modulator with DEM for multibit DACs

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A 0.4 V 63 <formula formulatype="inline"><tex Notation="TeX">$\mu$</tex></formula>W 76.1 dB SNDR 20 kHz Bandwidth Delta-Sigma Modulator Using a Hybrid Switching Integrator

Cited by 24 publications

References 33 publications

A 103 dB DR Fourth-Order Delta-Sigma Modulator for Sensor Applications

A 103 dB DR Fourth-Order Delta-Sigma Modulator for Sensor Applications

A 0.4-V 0.2 pJ/step 90-dB SNDR 20-kHz CT delta-sigma modulator using class-AB amplifier with a novel local common-mode feedback

A 15‐MHz bandwidth double sampling MASH25b‐15b sigma‐delta modulator with DEM for multibit DACs

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A 15‐MHz bandwidth double sampling MASH2_5b‐1_5b sigma‐delta modulator with DEM for multibit DACs