A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration

Kaviani, K.; Amirkhany, Amir; Huang, Ching-Chao; Le, Phuong; Madden, Chris; Saito, Keisuke; Sano, Koji; Murugan, V.; Beyene, W.T.; Chang, Ken; Yuan, Chuck

doi:10.1109/isscc.2012.6176950

Cited by 14 publications

(5 citation statements)

References 4 publications

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“…Several innovative circuit and architecture features have been described, including an active-inductor CTLE that directly interfaces to the sampling latch, low-latency serializer and deserializer, and a phase rotator based on current-integrating phase interpolators with improved linearity and supply rejection as compared to prior art [2]. Table 1 compares this work with recent I/Os operating near 16Gb/s [7][8][9][10]. This work achieves better than 2pJ/b power efficiency while equalizing 10dB of channel loss, making this suitable for source-synchronous power critical applications with short-to-moderate reach.…”

Section: Discussionmentioning

confidence: 99%

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

Dickson

Liu

Agrawal

et al. 2015

2015 IEEE Custom Integrated Circuits Conference (CICC)

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A 16x16-Gb/s source-synchronous I/O is reported in 32nm SOI CMOS. The bus-level receiver includes redundant RX lanes to enable lane recalibration with reduced power and area overhead. The I/O also includes an 8:1 TX serializer with 8-phase clocking, and an active-inductor-based RX CTLE whose outputs form current mirrors with the inputs of the RX samplers. A phase rotator based on currentintegrating phase interpolator cores is described, with architecture and circuit improvements to performance as compared to prior art. 16-Gb/s link measurements over Megtron-6 traces demonstrate efficiencies of 1.8pJ/bit (0.75" traces) and 1.9pJ/bit (10" traces) with >30% timing margin, with the TX, RX, and PLL operating from 1V supplies.

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Section: Discussionmentioning

confidence: 99%

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

Dickson

Liu

Agrawal

et al. 2015

2015 IEEE Custom Integrated Circuits Conference (CICC)

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“…Figure 1 plots energy per bit transfer (pJ/bit) versus bit rate per pin (Gbps/pin) of recent parallel and serial interfaces [9,10,11,12,13,14,15,16,17,18]. The serial interface can provide much higher Gbps/pin at lower pJ/bit than the parallel interface, consuming lower I/O power (Gbps × pJ/bit).…”

Section: Introductionmentioning

confidence: 99%

Alloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systems

Wang

Park

Byun

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

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A single-chip heterogeneous processor integrates both CPU and GPU on the same chip, demanding higher memory bandwidth. However, the current parallel interface (e.g., DDR3) can increase neither the number of (memory) channels nor the bit rate of the channels without paying high package and power costs. In contrast, the high-speed serial interface (HSI) can offer much higher bandwidth for the same number of pins and lower power consumption for the same bandwidth than the parallel interface. This allows us to integrate more channels under a pin and/or package power constraint but at the cost of longer latency for memory accesses and higher static energy consumption in particular for idle channels. In this paper, we first provide a deep understanding of recent HSI exhibiting very distinct characteristics from past serial interfaces in terms of bit rate, latency, energy per bit transfer, and static power consumption. To overcome the limitation of using only parallel or serial interfaces, we second propose a hybrid memory channel architecture-Alloy consisting of lowlatency parallel and high-bandwidth serial channels. Alloy is assisted by our two proposed techniques: (i), a memory channel partitioning technique adaptively maps physical (memory) pages of latency-sensitive (CPU) and bandwidthconsuming (GPU) applications to parallel and serial channels, respectively, and (ii) a power management technique reduces the static energy consumption of idle serial channels. On average, Alloy provides 21% and 32% higher performance for CPU and GPU, respectively, while consuming total memory interface energy comparable to the baseline parallel channel architecture for diverse mixes of co-running CPU and GPU applications. Keywords Memoryarchitecture; Serial memory interface; Heterogeneous processors 978-1-4799-8930-0/15/$31.00 ©2015 IEEE

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“…1) Historically, high-speed interconnect technologies have been using solid wire lines and connectors with metal contacts. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15] Impedance mismatch at the connector causes multi-reflections and the loss component of the channel causes notable inter symbol interference (ISI). In addition, exposed metal terminals in conventional systems need strong electro static discharge (ESD) protection devices causing worse signal integrity and input/output (I/O) power increment.…”

Section: Introductionmentioning

confidence: 99%

A 3 Gbps Non-Contact Inter-Module Link with Twofold Transmission Line Couplers and Low Frequency Compensation Equalizer

Kosuge¹,

Takeya²,

Shioya³

et al. 2013

Jpn. J. Appl. Phys.

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A non-contact inter-module link technique which consists of transmission line couplers (TLCs) and an equalizing receiver is proposed. The non-contact interface allows eliminating metal terminals and eases electro-static discharge (ESD) protection constraints, leading to higher channel bandwidth. Signals pass through two TLCs via a transmission line so that they are differentiated twice (d 2 v/d t 2) and turn into double-peak pulses. To retrieve original waveforms, we developed a low-frequency compensation continuous time linear equalizer (LFC-CTLE) to emphasize the low frequency part converting the double-peak pulses to the first order differentiated shapes, resulting in improving the data rate. To verify this technique, we designed and fabricated a test chip in 0.18 µm CMOS technology and we achieved 3 Gbps data rate at the bit error rate of (BER) less than 10-11 with a 10-in. long FR4 micro strip line and two 11 mm length TLCs.

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A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration

Cited by 14 publications

References 4 publications

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

Alloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systems

A 3 Gbps Non-Contact Inter-Module Link with Twofold Transmission Line Couplers and Low Frequency Compensation Equalizer

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A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration

Cited by 14 publications

References 4 publications

A 1.8-pJ/bit 16&#x00D7;16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

A 1.8-pJ/bit 16&#x00D7;16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

Alloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systems

A 3 Gbps Non-Contact Inter-Module Link with Twofold Transmission Line Couplers and Low Frequency Compensation Equalizer

Contact Info

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A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration