A 0.5-V 25-MHz 1-mW 256-Kb MTCMOS/SOI SRAM for Solar-Power-Operated Portable Personal Digital Equipment—Sure Write Operation by Using Step-Down Negatively Overdriven Bitline Scheme

Shibata, Noriyoshi; Kiya, H.; Kurita, Shigehiro; Okamoto, H.; Tanno, Masaaki; Douseki, Takakuni

doi:10.1109/jssc.2005.864124

Cited by 72 publications

(37 citation statements)

References 23 publications

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“…The second method is to collapse V DD , which weakens the pull-up transistors [4,9,10]. The third and fourth methods involve strengthening the pass-gate transistors by either boosting the WL V DD or reducing the BL V SS [4][5][6][7][8]11,13]. These methods strengthen the passgate by increasing its V GS .…”

Section: Write Assist Methodsmentioning

confidence: 99%

“…The downside to this strategy is that adding more transistors to the bitcell increases the total area of the array. The second strategy is to use various assist methods [4][5][6][7][8][9][10][11][12][13] to make the cell easier to read and write. This method also results in a smaller area overhead and may require multiple voltage sources.…”

Section: Introductionmentioning

confidence: 99%

“…This paper provides a comparison of four different bitcell topologies using read and write V MIN as the metrics for evaluation. In addition, read and write assist methods were tested using the periphery voltage scaling techniques discussed in [4][5][6][7][8][9][10][11][12][13]. Measurements taken from a 180 nm test chip show read functionality (without assist methods) down to 500 mV and write functionality down to 600 mV.…”

mentioning

confidence: 99%

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Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

Boley

Wang

Calhoun

2012

JLPEA

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Abstract:The need for ultra low power circuits has forced circuit designers to scale voltage supplies into the sub-threshold region where energy per operation is minimized [1]. The problem with this is that the traditional 6T SRAM bitcell, used for data storage, becomes unreliable at voltages below about 700 mV due to process variations and decreased device drive strength [2]. In order to achieve reliable operation, new bitcell topologies and assist methods have been proposed. This paper provides a comparison of four different bitcell topologies using read and write V MIN as the metrics for evaluation. In addition, read and write assist methods were tested using the periphery voltage scaling techniques discussed in [4][5][6][7][8][9][10][11][12][13]. Measurements taken from a 180 nm test chip show read functionality (without assist methods) down to 500 mV and write functionality down to 600 mV. Using assist methods can reduce both read and write V MIN by 100 mV over the unassisted test case.

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Section: Write Assist Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

Boley

Wang

Calhoun

2012

JLPEA

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“…The read disturb problem can be mitigated by adding a dedicated read port to isolate the bitcell internal nodes from the bitlines, but these resulting 7T, 8T, 9T and 10T SRAM bitcells [9][10][11][12][13] occupy larger area. The access-disturbance margin (ADM) can be improved by reducing the amount of charge injection from the pre-charged bitline to the '0' node of the active bitcell.…”

Section: Read Assist Schemesmentioning

confidence: 99%

A 28-nm 32Kb SRAM For Low-VMIN Applications Using Write and Read Assist Techniques

Kumar¹,

Saha²,

Gupta³

2017

RADIOENGINEERING

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“…Fig. 19(d) investigates write assist using negative voltage levels on the bit-lines [30]. A 100 mV negative bit-line bias results in a significant improvement in .…”

Section: E Impact Of Assist Techniquesmentioning

confidence: 99%

Characterization of Dynamic SRAM Stability in 45 nm CMOS

Toh

Guo

Liu

et al. 2011

IEEE J. Solid-State Circuits

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Abstract-Optimization of SRAM yield using dynamic stability metrics has been evaluated in the past to ensure continued scaling of bitcell size and supply voltage in future technology nodes. Various dynamic stability metrics have been proposed but they have not been used in practical failure analysis and compared with conventional static margins. This work compares static and dynamic metrics to identify expected correlations. A dynamic stability characterization architecture using pulsed word-lines is implemented in 45 nm CMOS to identify sources of variability, and their impact on SRAM stability. Static read margins were observed to overestimate failures by 10-100 X while static write margins failed to predict outliers in critical writeability. Critical writeability was demonstrated to exhibit an enhanced sensitivity to process variations, random telegraph noise (RTN), and negative bias temperature instability (NBTI), compared to static write margins.

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A 0.5-V 25-MHz 1-mW 256-Kb MTCMOS/SOI SRAM for Solar-Power-Operated Portable Personal Digital Equipment—Sure Write Operation by Using Step-Down Negatively Overdriven Bitline Scheme

Cited by 72 publications

References 23 publications

Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

A 28-nm 32Kb SRAM For Low-VMIN Applications Using Write and Read Assist Techniques

Characterization of Dynamic SRAM Stability in 45 nm CMOS

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