A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling

All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector

“…Input signal is sampled by sampler [22], the sampled signals (D n , E n ) are input to the dual-mode phase detection logic circuits to generate early and late signal ( Fig. 1(a)) [23,24,25]. The phase-detection logic circuits generate two sets of phase error signals E IAPD =L IAPD and E ABPD =L ABPD according to its input-output characteristic respectively.…”

A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner

“…It is shown in Fig. 3 that the architecture of the conventional CDR can be classed by two types: the phase tracking CDR [6−9] and the phase picking CDR [10,11] . In the phase tracking CDR, the phase detector (PD) continuously measures the phase relation between the coming date (data) and the sample clock (cks).…”

Dual-Delay-Path Ring Oscillator with Self-Biased Delay Cells for Clock Generation

“…Oscillating structure design plays a critical role in the telecommunication systems operation [1]. In this context, voltage-controlled oscillators (VCO) are applied in analog-to-digital converters (ADC), in phase-locked loop (PLL)-based frequency synthesizers (FS) for clock and data recovery circuits (CDR) in serial data communication [2] [3], disk-drive read channels [4], on-chip clock distribution [5], and also for the local oscillator (LO) signal generation in radio frequency RF transceivers [6]. When compared with LC tank resonance-based oscillators, the set of structure and operating features of ring oscillators involves higher integration level in CMOS-based technologies (smaller area), the possibility of voltage or cur-rent-based frequency control, extended linearity and wider tuning range.…”