A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC

Kim, Min; Ahn, Gil-Cho; Hanumolu, Pavan Kumar; Lee, Sang-Hyeon; Kim, Sang-Ho; You, Seung-Bin; Kim, Jae-Whui; Temes, Gábor C.; Moon, Un-Ku

doi:10.1109/jssc.2008.920329

Cited by 59 publications

(16 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…1 [8]. A single-loop and single-bit architecture is employed to achieve the high-resolution without imposing severe matching requirements for the circuitry [9].…”

Section: Modulator Architecture and Circuit Implementationmentioning

confidence: 99%

A 1.8 V 89.2 dB dynamic range delta-sigma modulator using an op-amp dynamic current biasing technique

Kwak

Cho

Kim

et al. 2017

IEICE Electron. Express

Self Cite

View full text Add to dashboard Cite

A third-order single-bit delta-sigma modulator is presented in this paper. An op-amp dynamic current biasing technique is used to improve the power-efficiency of the modulator. The voltage reference block is integrated with the delta-sigma modulator core to avoid the use of large off-chip bypass capacitors and to minimize pin numbers. It achieves 89.2 dB dynamic range over 10 kHz signal bandwidth with an oversampling ratio of 128. The delta-sigma modulator core and on-chip voltage reference block consume 880 µW and 550 µW, respectively, from a 1.8 V power supply. The prototype chip occupies 1.26 mm 2 using a 0.18 µm CMOS technology.

show abstract

“…1 [8]. A single-loop and single-bit architecture is employed to achieve the high-resolution without imposing severe matching requirements for the circuitry [9].…”

Section: Modulator Architecture and Circuit Implementationmentioning

confidence: 99%

A 1.8 V 89.2 dB dynamic range delta-sigma modulator using an op-amp dynamic current biasing technique

Kwak

Cho

Kim

et al. 2017

IEICE Electron. Express

Self Cite

View full text Add to dashboard Cite

show abstract

“…If can be neglected, (10) and (11) indicate that of the CP integrator is 1/4 of the conventional integrator.…”

Section: A Linear Feedback Modelmentioning

confidence: 99%

“…To reduce the power consumption within the scope of ADCs several techniques have been utilized. Double sampling effectively halves the required ADC sampling-rate, hence reduces its power consumption [8]- [10]. OTA sharing has allowed the implementation of ADCs with only one OTA [7], [11].…”

mentioning

confidence: 99%

A Low-Power Delta-Sigma Modulator Using a Charge-Pump Integrator

Nilchi

Johns

2013

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

Abstract-In this paper a low-power switched-capacitor integrator based on a capacitive charge-pump (CP) is presented, and its practical effects are discussed. The CP integrator is employed as the first stage of a ADC. The 0.13 m CMOS prototype of the CP based ADC achieves the same performance as a conventional ADC while consuming 66% lower OTA power in the front-end integrator. The CP based modulator realizes 87.8 dB SNDR, 89.2 dB SNR and 90 dB DR over a 10 kHz bandwidth with 148 W power consumption. The conventional ADC has similar performance but dissipates 241 W. The energy required per conversion-step for the CP based ADC (0.369 pJ/step) is almost 40% lower than that of the conventional ADC (0.607 pJ/step).

show abstract

“…However, as mentioned, a conventional delta-sigma modulator cannot easily be power-scaled, necessitating the use of an incremental converter. JSSC'04 [12] ISSCC'05 [11] ISSCC'06 [10] JSSC'09 [6] JSSC'08 [9] JSSC'97 [8] JSSC'01 [13] This Work This Work …”

Section: A Delta-sigma Modulatormentioning

confidence: 99%

A frequency-scalable 15-bit incremental ADC for low power sensor applications

Liang

Johns

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

View full text Add to dashboard Cite

Abstract-A 15-bit low-power incremental ADC is designed for sensor applications. The ADC is designed to be frequency-scalable by 1000 times from 1.67S/s to 1.67kS/s. To reduce power, an opamp with class AB characteristics is used. The design was fabricated in 0.18μm CMOS and occupies an area of 0.35mm 2 . Configured to operate at full-rate as a Delta-Sigma modulator, the ADC achieves 91.8dB peak SNDR while consuming 83μW from a 1.8-V supply. Operating as an incremental converter, the ADC powers off periodically to achieve frequency scalability, maintaining 84.7dB to 88.9dB peak SNDR while operating from 1.67S/s to 1.67kS/s and scaling analog power by up to 500 times.

show abstract

A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC

Cited by 59 publications

References 17 publications

A 1.8 V 89.2 dB dynamic range delta-sigma modulator using an op-amp dynamic current biasing technique

A 1.8 V 89.2 dB dynamic range delta-sigma modulator using an op-amp dynamic current biasing technique

A Low-Power Delta-Sigma Modulator Using a Charge-Pump Integrator

A frequency-scalable 15-bit incremental ADC for low power sensor applications

Contact Info

Product

Resources

About