A 1.2 μm CMOS implementation of a low-power 900-MHz mobile radio frequency synthesizer

Thamsirianunt, M.; Kwaśniewski, T.

doi:10.1109/cicc.1994.379683

Cited by 15 publications

(4 citation statements)

References 6 publications

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“…The authors are currently working on the evaluation of a complete fractional-N synthesizer [23]. Such a synthesizer might exhibit power consumption below 10 mW, one gigahertz maximum operating frequency, and be suitable for use in the personal communication devices.…”

Section: Discussionmentioning

confidence: 99%

CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communications

Thamsirianunt¹,

Kwaśniewski

1997

IEEE J. Solid-State Circuits

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CMOS inductorless voltage controlled oscillator (VCO) design is discussed with the emphasis on low-noise, low-power, gigahertz-range circuits suitable for portable wireless equipment. The paper considers three VCO structures-one simple ring oscillator and two differential circuits. The design methodology followed optimization for high-speed and low-power consumption. The proposed linearized MOSFET model allows the accurate prediction of the operating frequency while the phase noise evaluation technique makes it possible to determine, through simulation, the relative phase-noise performance of different oscillator architectures. The measurement results of three VCO's implemented in 1.2-m CMOS technology confirm with the simulation predictions. The prototype VCO's exhibits 926-MHz operation with 083 dBc/Hz phase noise (@ 100 kHz carrier offset) and 5 mW (5 V) power consumption. Index Terms-CMOS oscillator, ECO, emitter coupled oscillator, linearized MOSFET model, multivibrator, phase locked loop, phase noise simulation, PLL frequency synthesizer, relaxation oscillator, ring oscillator, VCO, voltage controlled oscillator.

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Section: Discussionmentioning

confidence: 99%

CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communications

Thamsirianunt¹,

Kwaśniewski

1997

IEEE J. Solid-State Circuits

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“…RF VCO designs based upon integrated ring oscillator topologies [11] cannot achieve the stringent low phase noise requirement because this type of oscillator has an effective Q value about 1. The phase noise is primarily a function of power dissipation rather than electronic device characteristics [12].…”

Section: Rf Low Phase Noise Vcomentioning

confidence: 99%

A micromachined RF low phase noise voltage-controlled oscillator for wireless communications

Young

Boser

Malba

et al. 2001

Int J RF and Microwave Comp Aid Eng

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An RF low phase noise voltage-controlled oscillator is implemented with micromachined IC-compatible variable capacitors and three-dimensional coil inductor. Unlike conventional on-chip passive devices, the micromachined variable capacitors achieve a high-Q value above 60 at 1 GHz with a 15% tuning range for a nominal 2 pF capacitance with 3 V tuning voltage. Three-dimensional inductors minimize the substrate loss and achieve a Q of 30 at 1 GHz with a 4.8 nH inductance. Both passive components are fabricated on silicon substrates and thus amenable to monolithic integration with standard IC process. The prototype VCO exhibits −136 dBc/Hz phase noise at 3 MHz offset frequency from the carrier, suitable for most wireless communication applications, in particular GSM. The VCO is tunable from 855 Mhz to 863 MHz, limited by the test set-up.

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“…A 50% nominal duty cycle is desired to avoid the dead-zone of the PFD and thus reduce distortion of the modulation signal. The prototype used a PFD design from [16] to achieve this characteristic.…”

Section: B Analog Sectionmentioning

confidence: 99%

A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation

Perrott

Tewksbury

Sodini

1997

IEEE J. Solid-State Circuits

251

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A digital compensation method and key circuits are presented that allow fractional-N synthesizers to be modulated at data rates greatly exceeding their bandwidth. Using this technique, a 1.8-GHz transmitter capable of digital frequency modulation at 2.5 Mb/s can be achieved with only two components: a frequency synthesizer and a digital transmit filter. A prototype transmitter was constructed to provide proof of concept of the method; its primary component is a custom fractional-N synthesizer fabricated in a 0.6-m CMOS process that consumes 27 mW. Key circuits on the custom IC are an onchip loop filter that requires no tuning or external components, a digital MASH 6-1 modulator that achieves low power operation through pipelining, and an asynchronous, 64-modulus divider (prescaler). Measurements from the prototype indicate that it meets performance requirements of the digital enhanced cordless telecommunications (DECT) standard.

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A 1.2 μm CMOS implementation of a low-power 900-MHz mobile radio frequency synthesizer

Cited by 15 publications

References 6 publications

CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communications

CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communications

A micromachined RF low phase noise voltage-controlled oscillator for wireless communications

A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation

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