A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13¿m CMOS

Clara, Martin; Klatzer, W.; Seger, B.; Giandomenico, A. Di; Gori, L.

doi:10.1109/isscc.2007.373388

Cited by 28 publications

(15 citation statements)

References 2 publications

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“…We concluded with a SFDR comparison with state-of-the-art CMOS DACs at similar sampling rate (f s ), as shown in Fig.5. Compared to the DACs with conventional calibrations [1][2], this work achieves much better SFDR and maintains above 78dBc in the whole Nyquist band. Compared to the best published DEM DAC [5], this work has 21dB better NSD and comparable SFDR.…”

Section: Discussionmentioning

confidence: 99%

“…A 14b 200MS/s DAC with SFDR>78dBc, IM3<-83dBc and NSD<-163dBm/Hz across the whole Nyquist Band enabled by Dynamic-Mismatch Mapping Introduction Process variation and layout asymmetry in current sources, latches, clock distribution etc., are error sources that result in amplitude & timing mismatch errors in a DAC and limit the performance [1][2][3][4][5][6]. Existing calibration techniques only focus on amplitude errors, such as trimming current sources [1][2] and static-mismatch mapping (SMM) [3]. However, as signal and sampling frequencies increase, the effect of timing errors will dominate that of the amplitude errors.…”

Section: Fig1 Dynamic Mismatchmentioning

confidence: 99%

“…Obviously, compared to static mismatch, dynamic mismatch represents the matching of switched-current cells more completely and accurately. Compared to that static mismatch can be easily measured in time domain [1][2], dynamic mismatch can be measured more efficiently in frequency domain. By modulating a current cell (cell n ) as rectangular-wave output at a frequency (f m ), its dynamic-mismatch error, relative to a reference cell (cell ref ), appears at all harmonic frequencies as shown in Fig.1(b).…”

Section: Dynamic-mismatch Mapping (Dmm)mentioning

confidence: 99%

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A 14b 200MS/s DAC with SFDR>78dBc, IM3<−83dBc and NSD<−163dBm/Hz across the whole Nyquist band enabled by dynamic-mismatch mapping

Tang

Briaire

Doris

et al. 2010

2010 Symposium on VLSI Circuits

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Section: Discussionmentioning

confidence: 99%

Section: Fig1 Dynamic Mismatchmentioning

confidence: 99%

Section: Dynamic-mismatch Mapping (Dmm)mentioning

confidence: 99%

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A 14b 200MS/s DAC with SFDR>78dBc, IM3<−83dBc and NSD<−163dBm/Hz across the whole Nyquist band enabled by dynamic-mismatch mapping

Tang

Briaire

Doris

et al. 2010

2010 Symposium on VLSI Circuits

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show abstract

“…Some more intricate solutions as: -a ΣΔ calibration analog to digital converter used for measuring the mismatch between current sources coupled with a calibration DAC which applies the correction [2], -using an analog calibration loop for each current source [3], -minimization of the "dynamic INL" related to the mismatch between the transients resulting when a certain current source is connected to the positive output node and to the negative output node [4] have been developed.…”

Section: Introductionmentioning

confidence: 99%

A new calibration method for current steering DACs

Brinzei

Constantinescu

2013

2013 4th International Symposium on Electrical and Electronics Engineering (ISEEE)

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A new calibration method for current steering DACs (digital to analog converters), whose main idea is to add compensation currents of the same value to the most sensitive current sources, is proposed. Some DC Monte-Carlo analyses are used to choose the optimal value for the correction current. The choice of the most sensitive current sources as well as the finding of the optimal combination of the corrected sources are done by steady state simulations and measurements. The SFDR (spurious free dynamic range) of a 8 bits DAC is improved with 5.5 dB using this method.

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“…Dynamic element matching is another technique that randomizes the selection of the sub-elements so that any mismatch among them appears as random noise. Also in digital calibration loops, it has been reported that randomizing the calibration period can help reduce undesired harmonic tones that arise due to periodicity [13].…”

Section: Introductionmentioning

confidence: 99%

Stochastic steady-state and AC analyses of mixed-signal systems

Kim

Ren

Horowitz

2009

Proceedings of the 46th Annual Design Automation Conference

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This paper demonstrates that the steady-state and adjoint sensitivity analyses can be extended to stochastic mixed-signal systems based on Markov chain models. The examples of such systems include digital phase-locked loops and delta-sigma data converters, of which steady-state response is statistical in nature, consisting of an ensemble of waveforms with probability distribution. For efficient Markov-chain analysis, the paper describes three methods that can limit the number of states: a state discretization scheme based on Gaussian decomposition, a state exploration algorithm that discovers the recurrent states, and a state truncation algorithm that eliminates the states with negligible stationary probabilities. The stochastic AC analysis is performed by deriving a first-order ordinary differential equation governing the perturbations in the stationary probabilities and solving it via phasor analysis. In the digital PLL and first-order '6 ADC examples, the number of states was reduced by a factor of 35 and the frequency-domain phase and noise transfer functions were simulated with a 57~22,000u speed-up compared to using transient, Monte-Carlo simulations.

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A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13¿m CMOS

Cited by 28 publications

References 2 publications

A 14b 200MS/s DAC with SFDR>78dBc, IM3<−83dBc and NSD<−163dBm/Hz across the whole Nyquist band enabled by dynamic-mismatch mapping

A 14b 200MS/s DAC with SFDR>78dBc, IM3<−83dBc and NSD<−163dBm/Hz across the whole Nyquist band enabled by dynamic-mismatch mapping

A new calibration method for current steering DACs

Stochastic steady-state and AC analyses of mixed-signal systems

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A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13¿m CMOS

Cited by 28 publications

References 2 publications

A 14b 200MS/s DAC with SFDR&#x003E;78dBc, IM3&lt;&#x2212;83dBc and NSD&lt;&#x2212;163dBm/Hz across the whole Nyquist band enabled by dynamic-mismatch mapping

A 14b 200MS/s DAC with SFDR&#x003E;78dBc, IM3&lt;&#x2212;83dBc and NSD&lt;&#x2212;163dBm/Hz across the whole Nyquist band enabled by dynamic-mismatch mapping

A new calibration method for current steering DACs

Stochastic steady-state and AC analyses of mixed-signal systems

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A 14b 200MS/s DAC with SFDR>78dBc, IM3<−83dBc and NSD<−163dBm/Hz across the whole Nyquist band enabled by dynamic-mismatch mapping

A 14b 200MS/s DAC with SFDR>78dBc, IM3<−83dBc and NSD<−163dBm/Hz across the whole Nyquist band enabled by dynamic-mismatch mapping