A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing

Yang, Jing; Naing, Thura Lin; Brodersen, R.W.

doi:10.1109/jssc.2010.2048139

Cited by 94 publications

(39 citation statements)

References 19 publications

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“…Assuming that the comparator has a typical single-pole response, the transfer function can be modeled as follows: (1) where is the comparator gain, is the comparator input voltage, and is the time constant. While naturally exponential, this delay is shown to vary linearly with the full-scale voltage of each stage (which scales down by a factor of two per stage) in the SAR operation as follows: (2) where is simply a constant term. This variation is plotted in Fig.…”

Section: Sar Quantizer Transient Responsementioning

confidence: 99%

“…The asynchronous SAR was demonstrated in [1] and can increase the effective overall speed of a SAR conversion by about a factor of two. However, the issue of missing bits due to midcycle metastability leads to either a larger bit error rate (BER) or increased critical path logic [2]. The variable window function SAR [3] reduces the required amount of switching to minimize the SAR input voltage, but requires extra voltage comparators and references with an accuracy that increases in each stage.…”

Section: Introductionmentioning

confidence: 99%

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A 10-b Ternary SAR ADC With Quantization Time Information Utilization

Guerber

Venkatram

Gande

et al. 2012

IEEE J. Solid-State Circuits

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The design of a ternary successive approximation (TSAR) analog-to-digital converter (ADC) with quantization time information utilization is proposed. The TSAR examines the transient information of a typical dynamic SAR voltage comparator to provide accuracy, speed, and power benefits. Full half-bit redundancy is shown, allowing for residue shaping which provides an additional 6 dB of signal-to-quantization-noise ratio (SQNR). Synchronous quantizer speed enhancements allow for a shorter worst case conversion time. An increased monotonicity switching algorithm, stage skipping due to reference grouping, and SAR logic modifications minimize overall dynamic energy. The architecture has been shown to reduce capacitor array switching power consumption and digital-to-analog converter (DAC) driver power by about 60% in a mismatch limited SAR, reduce comparator activity by about 20%, and require only 8.03 average comparisons and 6.53 average DAC movements for a 10-b ADC output word. A prototype is fabricated in 0.13-m CMOS employing on-chip statistical time reference calibration, supply variability from 0.8 to 1.2 V, and small input signal power scaling. The chip consumes 84 W at 8 MHz with an effective number of bits of 9.3 for a figure of merit of 16.9 fJ/C-S for the 10-b prototype and 10.0 fJ/C-S for a 12-b enhanced prototype chip.Index Terms-Residue shaping, successive approximation analog-to-digital converter (SAR ADC), SAR ADC redundancy, SAR switching, ternary SAR (TSAR), time quantization.

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Section: Sar Quantizer Transient Responsementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 10-b Ternary SAR ADC With Quantization Time Information Utilization

Guerber

Venkatram

Gande

et al. 2012

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

show abstract

“…The backend T/H is then followed by preamplifiers which are implemented by differential pairs with reset function to reduce memory effects between samples. The reset is controlled by a semi-synchronized (rising edge asynchronized while falling edge synchronized) logic circuit similar to the one reported in [37] which senses the output of the comparator and activates the reset switch as soon as the comparator makes a decision. The MUX for the adaptive signal paths selection is placed between the first preamplifier and the second preamplifer to avoid disturbing the high speed sampling operation which would lead to linearity degradation of the sampled signal (such as reducing tracking time and unwanted charge sharing).…”

Section: A Parallel-sampling Frontend Stage For a Ti-sar Adcmentioning

confidence: 99%

Implementations of the Parallel-Sampling ADC Architecture

Lin

Hegt

Doris

et al. 2015

Analog Circuits and Signal Processing

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This chapter describes circuit implementations of the parallel-sampling ADC architecture presented in Chap. 3. The parallel-sampling architecture is applied to two ADC architectures (a pipeline and a time-interleaving SAR ADC architecture), which are suitable for designing high-speed and medium-to-high resolution ADCs, to improve the ADC power efficiency for multi-carrier signals. Section 4.1 describes the architecture and operation of a 200 MS/s 12-b switchedcapacitor pipeline ADC with a parallel-sampling first stage, which is suitable for broadband multi-carrier receivers for wireless standards such as LTE-advanced and the emerging generation of Wi-Fi (IEEE802.11ac) . A circuit implementation of the parallel-sampling first stage of the pipeline ADC is presented and simulation results are given. Section 4.2 presents the architecture and operation of a 4 GS/s 11 b timeinterleaved ADC with a parallel-sampling frontend stage, which targets wideband direct sampling receivers for DOCSIS 3.0 cable modems . Circuit implementation and simulation of the 4 GS/s parallel-sampling frontend stage are given. Due to the complexity of implementing the proposed 4 GS/s ADC on chip, a two-step design approach was adopted. In Sect. 4.3, a prototype IC of an 11 b 1 GS/s ADC with a parallel sampling architecture is presented, which serves as a first step to validate the parallel-sampling ADC concept and the performance of the high-speed parallelsampling frontend and detection circuits. In future work, the frontend stage of the IC can be interleaved by four times to achieve the aggregate sample rate of 4 GHz of the proposed ADC discussed in Sect. 4.2. Conclusions of this chapter are drawn in Sect. 4.4.

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“…A smart solution to the implementation of a radix < 2 SA ADC is shown in Fig. 6 [31], [36], [40], [81]. The radix can be adjusted by choosing α and β, and a simple switching sequence similar to that used in the binary SA ADCs can be applied.…”

Section: B Circuit Implementationmentioning

confidence: 99%

Non-binary Successive Approximation Analog-to-Digital Converters: A Survey

Waho

2014

2014 IEEE 44th International Symposium on Multiple-Valued Logic

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Low-power successive-approximation (SA) analogto-digital converters (ADCs) are attracting increasing attention these days in biomedical and sensor network applications. The binary search algorithm is one of the basic idea behind how they obtain a binary code representing an analog input. In practice, the imperfectness of analog circuit elements sometimes results in decision errors and decreases the resolution of A/D conversion. Thus, making accurate decisions using imperfect elements is a big challenge. This paper surveys one solution known as non-binary SA with redundancy as well as related topics and its application to state-of-the-art SA ADCs.

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A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing

Cited by 94 publications

References 19 publications

A 10-b Ternary SAR ADC With Quantization Time Information Utilization

A 10-b Ternary SAR ADC With Quantization Time Information Utilization

Implementations of the Parallel-Sampling ADC Architecture

Non-binary Successive Approximation Analog-to-Digital Converters: A Survey

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