A 10-Gb/s Inductorless CMOS Limiting Amplifier With Third-Order Interleaving Active Feedback

Abstract

This paper presents an inductorless circuit technique for CMOS limiting amplifiers. By employing the third-order interleaving active feedback, the bandwidth of the proposed circuit can be effectively enhanced while maintaining a suppressed gain peaking within the frequency band. Using a standard 0.18-m CMOS process, the limiting amplifier is implemented for 10-Gb/s broadband applications. Consuming a DC power of 189 mW from a 1.8-V supply voltage, the fabricated circuit exhibits a voltage gain of 42 dB and a 3-dB bandwidth of 9 GHz. With a 2 31 1 pseudo-random bit sequence at 10 Gb/s, the measured output swing and input sensitivity for a bit-error rate of 10 12 are 300 and 10 mV pp , respectively. Due to the absence of the spiral inductors, the chip size of the limiting amplifier including the pads is 0.68 0.8 mm 2 where the active circuit area only occupies 0.32 0.6 mm 2 .

A 1–13 Gbps tunable optical receiver with supply voltage scaling

“…Binary-to-thermometer conversion circuit is adopted to easily control the transimpedance gain. The active feedback topology is also exploited in the LMT with third-order interleaving technique to enhance the bandwidth [5], as shown in Fig. 1(c).…”

A 10Gb/s two dimensional scanning eye opening monitor in 0.18um CMOS process

“…This circuit provides a good bandwidth and gain performance without the use of any inductor [7]. The topology of the third-order interleaved feedback is shown in fig 5. The component amplifiers are fully differential.…”

8.4 A 28Gb/s 1pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28nm CMOS

“…Broadband techniques such as inductive peaking are commonly used in highspeed optical transceivers for bandwidth enhancement at the expense of the chip area. Inductor-less receivers have been proposed [4,6] to reduce chip area but they usually consume more power or have lower data rates at given technology nodes.In this paper, we present two optical receivers that each consists of a pseudodifferential CMOS push-pull transimpedance amplifier (TIA), a DC offsetcancellation circuit, a limiting amplifier (LA) with interleaving active-feedback [6], and a T-Coil f T -doubler output buffer. The block diagram and experimental setup are shown in Fig.…”

“…Broadband techniques such as inductive peaking are commonly used in highspeed optical transceivers for bandwidth enhancement at the expense of the chip area. Inductor-less receivers have been proposed [4,6] to reduce chip area but they usually consume more power or have lower data rates at given technology nodes.…”

“…In this paper, we present two optical receivers that each consists of a pseudodifferential CMOS push-pull transimpedance amplifier (TIA), a DC offsetcancellation circuit, a limiting amplifier (LA) with interleaving active-feedback [6], and a T-Coil f T -doubler output buffer. The block diagram and experimental setup are shown in Fig.…”