A 100 MHz macropipelined CISC CMOS microprocessor

Badeau, R.; Bahar, R. Iris; Bernstein, D.; Biro, Larry; Bowhill, William J.; Brown, Jonathon D.; Case, Mike; Castelino, R.W.; Cooper, Elizabeth; Delaney, Marie; Deverell, D.R.; Edmondson, John H.; Ellis, J.; Fischer, T.C.; Fox, T.F.; Gowan, M.K.; Gronowski, P.E.; Herrick, W.V.; Jain, Alok; Meyer, J.; Miner, D.G.; Partovi, H.; Peng, V.; Preston, R.P.; Somanathan, C.; Stamm, Rebecca L.; Thierauf, Stephen C.; Uhler, M.; Wade, N.D.; Wheeler, William

doi:10.1109/isscc.1992.200433

Cited by 7 publications

(2 citation statements)

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“…These challenges are intensified by the need to bring designs to market quickly. This paper describes Digital Equipment Corporation's approach to high-performance microprocessor design as practiced on projects such as the 100 MHz CISC NVAX microprocessor [1] and the 200 MHz RISC Alpha AXP 21064 microprocessor [2]. Summaries of the characteristics of these microprocessors are given in Tables I and II, and a description of the 0.75 micron CMOS-4 technology used to manufacture them is given in Table III.…”

Section: Introductionmentioning

confidence: 99%

The design of high-performance microprocessors at Digital

Fox

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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Abstract--Today's high-performance single-chip CMOS microprocessors are the most complex and challenging chip designs ever implemented. To stay on the leading edge, Digital's microprocessor designers strive for global optimizations across the design space, develop innovative highspeed custom circuit design techniques, and use state-of-the-art manufacturing technology for fabrication. With microprocessor performance increasing at a rate of 50% per year, quick time-to-market is crucial. Logic and circuit bugs that would prevent first-pass silicon from booting the operating system must be eliminated before tape out if unacceptable schedules delays are to be avoided. Quick time-to-market is achieved by: fostering good design practice through the use of a consistent methodology and detailed design reviews; accounting for manufacturing variations and long-term reliability concerns from the start of the design; and subjecting the chip models to rigorous logical and electrical verification prior to prototype fabrication. This paper presents a practical view of Digital's design process.

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Section: Introductionmentioning

confidence: 99%

The design of high-performance microprocessors at Digital

Fox

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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“…Adding decoupling bypass capacitors between power and ground is one of the most effective techniques. There are two ways to attach the decoupling capacitors close to the die: the offchip and the on-chip methods (See Figure 1) [1,2]. Both methods are already being used in the industry.…”

Section: Isbn# 0-7803-2639-3mentioning

confidence: 99%

Ground bounce study of 304 lead interposer MQFP with on-chip decoupling capacitor test die

Huang

Loh

Wong

IEEE Technical Applications Conference and Workshops. Northcon/95. Conference Record

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Bias 0.0v 0.3v San Jose, CA 95 13 1 (Tel) 408-434-32 8 5 1.ov 3.0v 5.ov ' 8.5 6.8 6.1 AbstractAs clock frequency and the number of YO'S increase in ASIC devices, the ground bounce problems of packages begin to seriously impact system performance. To resolve these problems, high performance packages must be used in system design. This, however, can add significantly to the cost of the system. One of the methods to optimize the cost, manufacturability and the performance of packages is to add decoupling capacitors to the power and the ground of the die or packages. However, adding decoupling capacitors always increases the inductance effects. A systematic approach is needed to determine the correct method of using the decoupling capacitor technique with minimal inductive effects. 0.0V 0.3V 1.0V 3.OV 5.OV

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