A 100mW 9.6Gb/s Transceiver in 90nm CMOS for Next-Generation Memory Interfaces

Prete, E.; Scheideler, D.; Sanders, A.

doi:10.1109/isscc.2006.1696055

Cited by 18 publications

(8 citation statements)

References 2 publications

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“…Links which leverage source synchronous clocking, such as high-bandwidth multichannel parallel connections from processor to processor or memory chips ( Figure 1) [3,4], have potential to achieve these objectives due to their wide bandwidth jitter tracking and reduced clock circuitry complexity relative to embedded clock systems [5].…”

Section: Introductionmentioning

confidence: 99%

Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links

Liu

Chiang

et al. 2011

Journal of Electrical and Computer Engineering

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High-speed links which employ source synchronous clocking architectures have the ability to track correlated jitter between clock and data channels up to high frequencies. However, system timing margins are degraded by channel skew between clock and data signals and high-frequency loss. This paper describes how these key channel effects impact the jitter performance and influence the clocking architecture of high-speed source synchronous links. Tradeoffs in complexity and jitter tracking performance of common per-channel de-skew circuits are discussed, along with how band-pass filtering can be leveraged to provide additional jitter filtering at the receiver. Jitter tolerance analysis for a 10 Gb/s system shows that a near all-pass delay-locked loop (DLL) and phase-interpolator-(PI-) based de-skew performs best under low skew conditions, while, at high skew, architectures which leverage band-pass clock filtering or a phase-locked loop (PLL) for increased jitter filtering are more suitable. De-skew based on injection-locked oscillators (ILOs) offer a reduced complexity design and competitive jitter tolerance over a wide skew range.

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Section: Introductionmentioning

confidence: 99%

Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links

Liu

Chiang

et al. 2011

Journal of Electrical and Computer Engineering

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“…In write operation, maximum turn-around time (T turn_around ) occurs when the write signal is sent from the controller to memory module #3. This time can be expressed as (5). T d is the flight time of the signal passing through each TL…”

Section: Impedance-matched Bidirectional Multidrop Dq Busmentioning

confidence: 99%

“…To fulfill demands on memory capacity per channel as well as high data-rate, daisy-chained point-to-point bus topologies such as fully buffered DIMM (FBDIMM) with an advanced memory buffer [4], [5] and a cascading memory architecture [6], [7] have been taken. However, these buses have an undesirably long latency.…”

Section: Introductionmentioning

confidence: 99%

4-Slot, 8-Drop Impedance-Matched Bidirectional Multidrop DQ Bus With a 4.8-Gb/s Memory Controller Transceiver

Shin

Hong

Lee

et al. 2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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In this paper, we introduce an impedance-matched bidirectional multidrop (IMBM) DQ bus, together with a 4.8-Gb/s transceiver for a memory controller that supports this bus. Reflective ISI is eliminated at each stub of the IMBM DQ bus by resistive unidirectional impedance matching. A prototype memory controller transceiver is designed and fabricated in a 0.13-µm CMOS process and operates with a 1.2-V supply voltage. Its effectiveness is shown on various multidrop channel configurations. At 4.8 Gb/s, this transceiver with a 4-slot, 8-drop IMBM DQ bus has an eye opening of 0.39 UI in TX mode and 0.58 UI in RX mode, at a threshold of 10 −9 BER, whereas a comparable transceiver with a conventional 4-slot, 8-drop stub series terminated logic has no timing margin under the same test conditions. Our transceiver consumes 14.25 mW/Gb/s per DQ in TX mode, and 13.69 mW/Gb/s per DQ in RX mode.Index Terms-High-speed interface, impedance matching, memory controller, memory interface, memory transceiver, multidrop DQ bus, stubseries terminated logic.

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“…The is commonly the product of the effective resistance and capacitance leading the "RC" nomenclature in the model. The delay is the well-known equation (2) Equation (2) is accurate only when is much less than the data rate. Fig.…”

Section: A Rc Delay Model For a Single-pole Systemmentioning

confidence: 99%

A Comprehensive Delay Model for CMOS CML Circuits

Seckin¹,

Yang

2008

IEEE Trans. Circuits Syst. I

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MOS-transistor-based current-mode logic (CML)-type (MCML) circuits in high-speed circuit applications often operate as low-swing analog circuits rather than fully switched digital circuits. At these high-speed operations, the effect of the finite input signal slope on the delay of MCML gates significantly increases mainly due to incomplete current steering. Hence, for such cases, the conventional RC delay model which is based on ideal step input assumption fails to track the delay of MCML circuits with errors as high as 40% when a design is optimized for high-speed. In this paper, a comprehensive delay model is proposed that accurately predicts the delay of MCML circuits for all types of operation from low-speed and fully switched to high-speed and low-swing applications by including the input slope effect (ISE) into the conventional RC delay model. Furthermore, the proposed model is extended to multilevel complex logic gates without losing the general RC delay model format. Theoretical results are compared with Spice simulations in a 0.13-m CMOS technology. Results show that the error in delay of the proposed model is less than 20% for all practical designs. The proposed model is still sufficiently tractable to be use in back-of-envelope calculations that achieve close-to-optimum solutions without running extensive parametric simulations. In addition to the achieved accuracy and preserved simplicity, the proposed model enhances the intuitive understanding of MCML gates that simple RC delay model fails to provide.

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A 100mW 9.6Gb/s Transceiver in 90nm CMOS for Next-Generation Memory Interfaces

Cited by 18 publications

References 2 publications

Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links

Receiver Jitter Tracking Characteristics in High-Speed Source Synchronous Links

4-Slot, 8-Drop Impedance-Matched Bidirectional Multidrop DQ Bus With a 4.8-Gb/s Memory Controller Transceiver

A Comprehensive Delay Model for CMOS CML Circuits

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