A 101 dB dynamic range, 2 kHz bandwidth delta-sigma modulator with a modified feed-forward architecture

Abstract

This paper presents a modified feed-forward (FF) delta-sigma modulator architecture that simplifies the switched-capacitor network of an analog adder in front of the quantizer. By eliminating the internal FF path from the first integrator output, the number of capacitors in the analog adder is reduced and the load capacitance of the first integrator becomes independent of the quantizer resolution. To verify the proposed modulator architecture, a three-bit second-order delta-sigma analog-to-digital converter (ADC) is implemented. The prototype ADC is fabricated in a 0.18 µm CMOS process with an active die area of 0.095 mm 2. It achieves a dynamic range (DR) of 101.0 dB and a peak signal-to-noise and distortion ratio (SNDR) of 97.1 dB in a 2 kHz signal bandwidth while consuming 63.4 µW from a 1.8 V/1.65 V power supply.

A 3rd-order 1-bit Σ-Δ modulator with a 2-tap FIR filter embedded

“…2.1 The modulator architecture When designing a low voltage Σ-Δ modulator, the feedforward topology is usually a good choice [10,11,12] for both power consumption and performance reasons: firstly, the output swings of the integrators are much smaller than those of feedback architecture, which means the total power consumption could be reduced. Secondly, the gain requirement for the operational amplifier is more relaxed than that of feedback architecture, which implies that there is no need to design a high-gain amplifier in low voltage environment [13,14,15].…”