A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration

Abstract

A 12 bit pipeline ADC with residue amplifiers calibrated for gain and distortion is presented. The settling accuracy of the residue amplifiers was lowered to achieve higher energy efficiency and the resulting errors were corrected in multiple stages using a split-ADC calibration technique. Starting from a typical op amp implementation, the settling accuracy of the residue amplifier was relaxed by a factor of more than 3x in the first two stages and by 2x in the remaining stages. The ADC was implemented in 40 nm digital CMOS and shows a Schreier figure-ofmerit of 157.5 dB at 1 V supply, sampling at 195 MS/s, with an SNDR/SFDR of 64.8 dB/82 dB. While working in continuous background mode, the split-ADC calibration improved the ADC SFDR by 37 dB within 70,000 samples.Index Terms-Analog-to-digital conversion, background calibration, class-A amplifier, nonlinearity calibration, pipelined ADC, settling accuracy, split-ADC, switched-capacitor circuits.

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