A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration

El-Chammas, Manar; Murmann, Boris

doi:10.1109/jssc.2011.2108125

Cited by 226 publications

(70 citation statements)

References 26 publications

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“…The calibration of timing skews in TI-ADCs is more complicated than offset and gain mismatch calibration. Many timing-skew calibration techniques have been proposed in theory, and have also been implemented on-chip or off-chip [16,29,59,60,66,67]. The key design considerations related to the clock signal generation for TI-ADCs are discussed in [65].…”

Section: Channel Timing Mismatch (Timing Skews)mentioning

confidence: 99%

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Zahrai

Onabajo

2018

JLPEA

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This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6-8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics.

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Section: Channel Timing Mismatch (Timing Skews)mentioning

confidence: 99%

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Zahrai

Onabajo

2018

JLPEA

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“…Electronics-only self-calibration techniques are desired for reduced calibration time and the cost of calibration. A lot of multi-channel skew self-calibration techniques have been reported in high-speed time-interleaved analog-to-digital converters (TiADCs) [8,9]. However, the techniques used in the TiADCs targeted for relatively small number of channels are not suitable for the column-parallel multi-channel skew calibration in TR imagers which have typically more than 100 columns.…”

Section: Introductionmentioning

confidence: 99%

A column-parallel clock skew self-calibration circuit for time-resolved CMOS image sensors

Miao

Yasutomi

Imanishi³

et al. 2015

IEICE Electron. Express

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This letter reports a column-parallel clock skew self-calibration circuit for time-resolved (TR) CMOS image sensors. In TR CMOS imagers, as the time resolution increases, the skew of gating clock between pixels becomes a difficult problem because the clock skew causes the reduction of measurable maximum range in particular pixels or unmeasurable pixels. To calibrate the skew in short time, a column-parallel skew self-calibration circuit based on two-stage delay line and a dual clock tree is proposed. The experimental results show that the skew calibration circuit successfully reduces the skew from 247 ps rms to 25 ps rms , and the calibration time is only 12 µs, which is much faster than the previous work.

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“…But this method suffers aliasing problem when applied to multi-channel cases and wide-band input signals. Alternatives based on statistics relax the constraints on input bandwidth [5]. But they ask for additional channel or need huge additional digital circuits.…”

Section: Introductionmentioning

confidence: 99%

“…One is to remove the sample-time error through extra complex digital process such as adaptive filter and blind equalization [6]. Another approach is to adjust the sampling clock delay path through digital-controlled delay element (DCDE) [5] which might worsen random jitter in clock path. This paper presents a mixed background technique to compensate sample-time error in TIADCs with low-complexity circuits and fastconvergence time.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, a voltage-controlled sampling switch implemented in the calibrated channel is used to correct the timing skew. The sampling switch does not add additional jitter and performs a good linearity with a big tuning range compared to traditional DCDE [5]. This calibration technique does not ask for extra calibration channel or high-performance digital elements as well.…”

Section: Introductionmentioning

confidence: 99%

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A mixed sample-time error calibration technique in time-interleaved ADCs

Chen

et al. 2013

IEICE Electron. Express

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Sample-time error between channels degrades resolution of time-interleaved analog-to-digital converters (TIADCs). A calibration method implemented in mixed circuits with low-complexity and fast-convergence is proposed in this paper. The algorithm for detecting sample-time error, which is widely applied to wide-sense stationary input signals, is based on correlation. The detected sample-time error is corrected by a voltage-controlled sampling switch. Experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise-and-distortion ratio improves 19.1 dB, and the spurious-free dynamic range improves 34.6 dB for a 70.12-MHz input after calibration. The convergence time of the calibration is about 20000 sampling intervals.

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A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration

Cited by 226 publications

References 26 publications

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

A column-parallel clock skew self-calibration circuit for time-resolved CMOS image sensors

A mixed sample-time error calibration technique in time-interleaved ADCs

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