A 14 bit self-calibrating charge redistribution SAR ADC

Haenzsche, Stefan; Henker, Stephan; Schüffny, René; Reichel, Thomas; Garzarolli, Matthias

doi:10.1109/iscas.2012.6271405

Cited by 8 publications

(4 citation statements)

References 5 publications

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“…To increase the margin by 1 time, the comparator input is designed to −8LSB to +8LSB sweeping range with a step of LSB/8, namely, -610μV to +610μV with a step of 9.5μV. Unlike auxiliary ADC calibration method [26,27], in this technique, to generate the comparator input voltage ranging, DAC capacitors are used in test mode [28,29,30]. The lowest three weighted capacitors (C17~C20) and fractional capacitors (C21~C24) in both P-side and N-side DAC are used.…”

Section: Comparator Noise Extraction Based On Statistical Residue Mea...mentioning

confidence: 99%

Comparator noise extraction and compensation technique for accuracy enhancement in 16 bit SAR ADC

Zhang,

Feng,

Zhao

et al. 2024

IEICE Electron. Express

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This paper presents a comparator noise extraction and compensation technique for accuracy enhancement utilized in 16-bit 1 MS/s fully-differential Successive-Approximation-Register Analog-to-Digital Converter (SAR ADC). Usually, 14.0-bit ENOB is easily achieved through capacitor mismatch and harmonic calibration. To decrease the noise further, comparator noise extraction technique which statistically estimates the comparator residue voltage is presented. All the measurement and correction process are on chip and in foreground. This technique is verified in a 0.18-μm 5 V CMOS process, and it measures a 2.6 dB SNR improvement and finally a 94.6 dB SNR is achieved with 1 MS/s sample clock and a 10 kHz input tone.

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Section: Comparator Noise Extraction Based On Statistical Residue Mea...mentioning

confidence: 99%

Comparator noise extraction and compensation technique for accuracy enhancement in 16 bit SAR ADC

Zhang,

Feng,

Zhao

et al. 2024

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…At the same time, the comparator input is disconnected from the main capacitor array, the capacitor lower plate is connected to ground, and the both capacitor arrays store the same charge. After that, the common mode is disconnected, and due to the presence of the comparator offset, an offset voltage Vos is superimposed on the Vip and Vin voltages, and the traditional dichotomy is used to complete the quantization of the comparator offset [8] .…”

Section: Comparator Offset Cancellationmentioning

confidence: 99%

Design of a 12 bit SAR ADC with Self-Calibration

Yu¹,

Luo²,

Gou³

2023

IJCATR

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Successive approximation analog-to-digital converter (SAR-ADC) are widely used in intelligent sensing fields due to it’s low power consumption, medium and high precision and such characteristics. Traditional binary SAR ADC have non-ideal factors such as DAC capacitor array mismatch and comparator offset, which severely limit it’s performance. Therefore, a self-calibration method for non-ideal factors is proposed in this work, and theoretical derivation and simulation analysis are carried out. A 12-bit non-binary SAR ADC with self-calibration is designed based on the TSMC 40nm CMOS process, which reduces the capacitance area, improves the conversion accuracy, and eliminates most of the errors caused by non-ideal factors. Simulation results show that the ADC’s SNDR is 72.01dB, and INL within +1.2/-1LSB, meets most of the market requirements.

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“…The foreground techniques require interruption of the operation of the ADC as can be seen in Fig. 5 [38], [48]- [54]. In Fig.…”

Section: Foreground and Background Calibrationmentioning

confidence: 99%

A Novel Built-in Self Calibration Technique to Minimize Capacitor Mismatch for 12-bit 32MS/s SAR ADC

Jung¹,

Kim²,

Kim³

2020

JICS

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This paper proposes a novel Built-in Self Calibration (BISC) technique for a 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The controller for the proposed algorithm operates as foreground operation to achieve low power consumption during operation. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 47% and 52%, respectively. The prototype was designed using 130nm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.6 dB and consumes 4.62 mW. The ADC core occupies an active area of only 240μmÍ 298 μm using 1.2V supply and the sampling rate of 50 MS/s.

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A 14 bit self-calibrating charge redistribution SAR ADC

Cited by 8 publications

References 5 publications

Comparator noise extraction and compensation technique for accuracy enhancement in 16 bit SAR ADC

Comparator noise extraction and compensation technique for accuracy enhancement in 16 bit SAR ADC

Design of a 12 bit SAR ADC with Self-Calibration

A Novel Built-in Self Calibration Technique to Minimize Capacitor Mismatch for 12-bit 32MS/s SAR ADC

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