A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI

Siddiqui, M. Sultan M.; Lee, Zhao Chuan; Kim, Tony Tae-Hyoung

doi:10.1109/tvlsi.2021.3102675

Cited by 12 publications

(6 citation statements)

References 33 publications

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“…Figure 14(a) plots HSNM and RSNM of 6 T SRAM cell with supply voltage varying from 0.25 V to 0.85 V. HSNM is defined as the measure of stability in standby mode whereas RSNM provides the read stability of an SRAM cell. WM plots for 6 T SRAM and recently reported 9 T SRAM [20] is shown in figure 15(b). The WM is defined as the difference between VDD and word line voltage at which nodes Q and QB flip.…”

Section: Stability Analysismentioning

confidence: 89%

“…Similarly, WM of read-buffer based SRAM cell will be same as that of conventional 6 T SRAM cell because all the read-buffer based SRAM cells use 6 T SRAM cell's differential write mechanism. Figure 14(b) shows that the WM of recently reported 9 T SRAM [20] is lower because this cell uses pseudodifferential write technique. The data is written into cell by always writing a '0' at the appropriate node.…”

Section: Stability Analysismentioning

confidence: 96%

“…However, bitline leakage issue remains there as was in CONV8T [16]. A recently reported 9 T SRAM cell [20] consists of 3 T read buffer, shown in figure 2(e), has an advantage of independent read port as compared to [16]. Additionally, this cell uses data aware write assist scheme for improving the write-ability.…”

Section: Existing Read Decoupled Cellsmentioning

confidence: 99%

“…Hence, the write-ability and read stability can be optimized independently, which facilitates a low-voltage operation [9]. Several SRAM designs with decoupled read port have been proposed to overcome the limitations in conventional 6 T SRAM [10][11][12][13][14][15][16][17][18][19][20][21][22][23][24]. Although read upset issue and reduced I ON /I OFF ratio issue have been subdued significantly, most of the cells still suffer from varying data-dependent leakage.…”

Section: Introductionmentioning

confidence: 99%

“…Along with the comprehensive analysis on the basis of read performance parameters of the proposed cell, an illustrative comparison with five previously reported read buffers (RB-A [16], RB-B [17], RB-C [18], RB-D [19], and RB-E [20]) and conventional 6 T SRAM cell has been presented and is compared on the basis of various performance parameters. The rest of the manuscript is organized as follows.…”

Section: Introductionmentioning

confidence: 99%

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A 9 T SRAM cell with data-independent read bitline leakage and improved read sensing margin for low power applications

Sharif¹,

Ahmad²,

Alam³

2022

Semicond. Sci. Technol.

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Read decoupled SRAM cells were proposed to address the conflicting Read and Write requirements in conventional 6T SRAM cells. However, even read decoupled SRAM cells face several challenges like degraded cell stability, data dependent read bitline (RBL) leakage, deteriorated RBL swing which causes the failure in read sensing at scaled voltages. Therefore, in this work, we propose a read decoupled 9T SRAM cell which improves the read performance. The proposed cell utilizes decoupled read port that significantly improves the read delay, ION/IOFF ratio, bitline leakage as compared to the existing read decoupled cells. The proposed read buffer, having only one transistor in the read path, offers much lower read delay as compared to the existing read buffers. The RBL leakage in the proposed design is also data independent, which significantly improves the RBL sensing margin. We analyse and compare the proposed SRAM cell with existing cells using HSPICE simulations with 16nm FinFET PTM technology. We observe that at a voltage of VDD = 0.35V, the proposed SRAM cell offers ~55% smaller read delay with only 8% increase in leakage power as compared to conventional 6T cell. However, the proposed SRAM cell incurs smallest leakage penalty and offers fastest read operation than the existing read buffer based SRAM cells. Attributed to the negligible bitline leakage in the proposed cell, it offers the highest RBL sensing voltage attributed to closeness of RBL voltage for read ‘1’ to VDD as compared with the other cells. Monte Carlo simulations are also carried out to confirm the robustness of the proposed design under PVT variations. We observe that the proposed SRAM cell is robust and supports voltage scaling and hence could be an attractive choice for low voltage and low power applications.

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Section: Stability Analysismentioning

confidence: 89%

Section: Stability Analysismentioning

confidence: 96%