A 2.2 W, 80 MHz superscalar RISC microprocessor

Gerosa, G.; Gary, S.; Dietz, C.; Pham, Dac; Hoover, K.; Álvarez, José Marcos Alonso; Sanchez, H.; Ippolito, P.; Ngo, Tai; Litch, S.; Eno, J.; Golab, J.; Vanderschaaf, N.; Kahle, J.

doi:10.1109/4.340417

Cited by 210 publications

(68 citation statements)

References 7 publications

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“…The maximum operating frequency of a system is determined by the latency of flip-flops as they are present at the starting and end points of signal delay paths (Yeap, 1998). TGFF belongs to the master-slave class of flip-flops which are generally used for low power applications (Gerosa et al, 1994). Moreover, TGFF is the best known flip-flop in terms of power-delay trade-off among all flip-flop categories.…”

Section: Transmission Gate Flip-flopmentioning

confidence: 99%

A comprehensive comparison between LE and LM-based methodologies for optimisation of digital circuits

Singh¹,

Tiwari²,

Gupta³

2013

IJCAD

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This paper presents a comprehensive comparison between Levenberg-Marquardt (LM) and logical effort (LE) theory-based optimisation techniques. While LM is a classical approach for optimisation and is embedded in SPICE, logical effort-based approach is contemporary, design specific and needs simple back of the envelope calculations for optimisation of digital circuits. Both the approaches have been used by digital circuit designers in the literature for comparing a proposed digital circuit with the existing designs while optimising any given design for timing, power and area parameters. The goal of writing this paper is to make digital system designers gain an insight into the procedures used for optimising digital circuits while at the same time a well-defined approach using LM algorithm is provided that can be easily automated with the current generation CAD tools. For the purpose of comparison some standard circuits were chosen and optimised for minimum PDP and PDAP. SPICE simulations have been extensively used for comparing the two methodologies in a 180 nm\1.8 V CMOS technology.Keywords: VLSI; digital CMOS circuits; logical effort theory; Levenberg-Marquardt algorithm; power-delay product; power-delay-area product.Reference to this paper should be made as follows: Singh, K., Tiwari, S.C. and Gupta, M. (2013) 'A comprehensive comparison between LE and LM-based methodologies for optimisation of digital circuits', Int.

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Section: Transmission Gate Flip-flopmentioning

confidence: 99%

A comprehensive comparison between LE and LM-based methodologies for optimisation of digital circuits

Singh¹,

Tiwari²,

Gupta³

2013

IJCAD

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“…The transmission-gate flip-flop with input gate isolation (TGFF) shown in Figure 3(a) is derived from the PowerPC603 latch-pair [2], where the input gate isolation is added for better noise immunity. An additional inverter at the output of the TGFF provides non-inverting operation.…”

Section: Flip-flop Topologies 31 Master-slave Latch Pairsmentioning

confidence: 99%

“…The most commonly used flip-flop design techniques are conventional master-slave latch-pairs [2,3] and pulse-triggered latches [4,5,6]. Other low-energy designs, often derived from the conventional techniques, use double-edge-triggering, reducedswing clock, or internal clock gating [7,8].…”

Section: Introductionmentioning

confidence: 99%

Analysis and design of low-energy flip-flops

Marković¹,

Nikolić²,

Brodersen³

ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581)

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This paper develops a methodology for selecting and optimizing flip-flops for low-energy systems with constant throughput. Characterization metrics, relevant to low-energy systems are discussed, providing insight into timing and energy parameters at both the circuit and system levels. Transistor sizes are optimized for minimal delay under constrained energy consumption. This methodology is applied to characterization of various flip-flop styles and their comparison in 0.25µm CMOS technology under scaled supply voltages. A transmission-gate master-slave latchpair has the largest internal race margin, lowest energy consumption, and has energy-delay product comparable to much faster pulse-triggered latches.

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“…Traditionally, the transmission-gate flip-flop (TGFF) has been used in standard cell design [11]. TGFF has a fully static master-slave structure by cascading two identical pass-gate latches and provide a short clock-to-output latency.…”

Section: B Flip-flop Designmentioning

confidence: 99%